9 research outputs found

    A formal approach to designing delay-insensitive circuits

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    Simulation Techniques

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    In the papers surveyed in this thesis a number of simulation techniques are presented together with their applications to several examples. The papers improve upon existing techniques and introduce new techniques. The improvement of existing techniques is motivated in programming methodology: It is demonstrated that existing techniques often introduce a double proof burden whereas the improved techniques alleviate such a burden. One application is to ensure delay insensitivity in a class of self-timed circuits. A major part of the thesis is concerned with the deduction and use of two simulation techniques to prove the correctness of translations from subsets of occam-2 to transputer code

    Parallel computations

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    The translation of processes into circuits

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    A process is a pair 〈 A, X 〉 in which A is a set of symbols (the alphabet) and X is a non-empty prefix-closed subset of A* (the trace set). A process may be viewed as the specification of a mechanism: -symbols correspond to events that may occur. -traces correspond to sequences of events that may be observed when the mechanism is in operation. In this paper we show how for a certain class of processes circuits can be derived that behave as prescribed by these processes. The circuits are delay-insensitive in the sense that their behaviour does not depend on delays in wires and switching elements. Events may be initiated by a mechanism (active events) or by the environment of the mechanism (passive events). It is shown how active events can be transformed into passive events, and vice versa. We show how the composition of processes corresponds to the composition of circuits

    The translation of processes into circuits

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    A process is a pair 〈 A, X 〉 in which A is a set of symbols (the alphabet) and X is a non-empty prefix-closed subset of A* (the trace set). A process may be viewed as the specification of a mechanism:\u3cbr/\u3e\u3cbr/\u3e -symbols correspond to events that may occur.\u3cbr/\u3e\u3cbr/\u3e -traces correspond to sequences of events that may be observed when the mechanism is in operation.\u3cbr/\u3e\u3cbr/\u3eIn this paper we show how for a certain class of processes circuits can be derived that behave as prescribed by these processes. The circuits are delay-insensitive in the sense that their behaviour does not depend on delays in wires and switching elements.\u3cbr/\u3e\u3cbr/\u3eEvents may be initiated by a mechanism (active events) or by the environment of the mechanism (passive events). It is shown how active events can be transformed into passive events, and vice versa.\u3cbr/\u3e\u3cbr/\u3eWe show how the composition of processes corresponds to the composition of circuits

    The translation of processes into circuits

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