Adaptive channels for wireless networks

Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (p. 71-73).by Andrew G. Chiu.S.B.and M.Eng

Parallel signal-processing for everyone

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (p. 65-67).We designed, implemented, and evaluated a signal-processing environment that runs on a general-purpose multiprocessor system, allowing easy prototyping of new algorithms and integration with applications. The environment allows the composition of modules implementing individual signal-processing algorithms into a functional application, automatically optimizing their performance. We decompose the problem into four independent components: signal processing, data management, scheduling, and control. This simplifies the programming interface and facilitates transparent parallel signal processing. For tested applications, our system both runs efficiently on single-processors systems and achieves near-linear speedups on symmetric-multiprocessor (SMP) systems.by Brett W. Vasconcellos.M.Eng

StreamIt: A Language and Compiler for Communication-Exposed Architectures

With the increasing miniaturization of transistors, wire delays are becoming a dominant factor in microprocessor performance. To address this issue, a number of emerging architectures contain replicated processing units with software-exposed communication between one unit and another (e.g., Raw, SmartMemories, TRIPS). However, for their use to be widespread, it will be necesary to develop a common machine language to allow programmers to express an algorithm in a way that can be efficiently mapped across these architectures. We propose a new common machine language for grid-based software-exposed architectures: StreamIt. StreamIt is a high-level programming language with explicit support for streaming computation. Unlike sequential programs with obscured dependence information and complex communication patterns, a stream program is naturally written as a set of concurrent filters with regular steady-state communication. The language imposes a hierarchical structure on the stream graph that enables novel representations and optimizations within the StreamIt compiler. We have implemented a fully functional compiler that parallelizes StreamIt applications for Raw, including several load-balancing transformations. Though StreamIt exposes the parallelism and communication patterns of stream programs, analysis is needed to adapt a stream program to a software-exposed processor. We describe a partitioning algorithm that employs fission and fusion transformations to adjust the granularity of a stream graph, a layout algorithm that maps a stream graph to a given network topology, and a scheduling strategy that generates a fine-grained static communication pattern for each computational element. Using the cycle-accurate Raw simulator, we demonstrate that the StreamIt compiler can automatically map a high-level stream abstraction to Raw. We consider this work to be a first step towards a portable programming model for communication-exposed architectures.Singapore-MIT Alliance (SMA

Functional Analysis of a SDR Based Bluetooth/HiperLAN Terminal Demonstrator

|In our Software Defined Radio (SDR) project we aim at combining two different types of standards, Bluetooth and HiperLAN/2 on one common hardware platform. HiperLAN/2 is a high-speed Wireless LAN (WLAN) standard, whereas Bluetooth is a low-cost and low-speed Personal Area Network (PAN) standard. An SDR system is a °exible radio system that is re-programmable and reconfigurable by software in order to cope with its multi-service, multi-standard and multi-band environment. Goal of our project is to generate knowledge about designing the front end of an SDR system where especially an approach from both analog and digital perspective is essential.To what extent can we use the HiperLAN/2 receiver hardware for our Bluetooth receiver? In this paper we present a functional architecture that brings the architectural descriptions of both standards to an equal level. This SDR functional architecture is used in the sequel of the project for a number of purposes, of which we mention 1. Definition of reference points (for requirements definition purposes). 2. Definition of interfaces (potential alignment with SDR Forum). 3. Delimitation of our demonstrator (what is it that is going to be built). 4. Identification of inter-standard functional integration challenges

Arquitetura de canais para rádios definidos por software de múltiplas camadas

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-graduação em Engenharia de Automação e Sistemas, Florianópolis, 2010Nos últimos anos, foram criados diversos padrões de redes sem fio para garantir o cumprimento de diferentes requisitos de alcance, vazão de dados, segurança e consumo de energia. Muitas vezes isso obriga a integração de componentes que suportam diversas redes sem fio para criação de equipamentos multipadrões. Essa solução tradicional, apesar de robusta, impõe uma série de limitações relacionadas com o espaço físico, consumo de energia e custo dos sistemas integrados, além da falta de flexibilidade para modificações. Uma alternativa a esse cenário tem sido o uso de Rádios Definidos por Software (SDR), os quais possuem a camada física completamente reconfigurável, permitindo flexibilidade em vários parâmetros de comunicação como faixa de freqüência, tipo de modulação e potência de transmissão. Atualmente, existem várias propostas para implementação de SDRs, destacando-se o GNU Radio em conjunto com a placa USRP como opção de baixo custo, que possibilita a criação de rádios funcionais a partir de modelos de alto nível utilizando computadores pessoais. Entretanto, existe uma lacuna no suporte nativo à implementação de múltiplas camadas físicas compartilhando a mesma interface física, o que causa um overhead maior que o desejado na criação de sistemas multipadrões. Para superar tal desafio, este trabalho apresenta a concepção de uma arquitetura de canais para múltiplas camadas físicas que se destaca por propor uma interface genérica que atende a todos os tipos de camadas físicas e pode ser suportada por diversos hardwares de SDR. Visando a melhor utilização dos recursos a arquitetura proposta permite o deslocamento do estágio de separação de múltiplos canais para o hardware sem a perda de flexibilidade. Para validar a arquitetura proposta foi desenvolvido um protótipo baseado no GNU Radio e USRP2, além das implementações de dois cenários de testes, com múltiplas camadas físicas iguais (IEEE802.15.4) e com múltiplas camadas diferentes (IEEE802.15.4 e IEEE802.11b). Os testes demonstraram uma melhora significativa no desempenho global do sistema e uma simplificação na interface com a camada física, uma vez que não há necessidade de configurar as variáveis relacionadas com os ajustes do próprio hardware

Software-based implementation of a frequency hopping two-way radio

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 105-107).by Alok B. Shah.M.Eng

Design of a Reconfigurable Multi-Core Architecture for Streaming Applications

This thesis presents design of a reconfigurable multi-processor architecture.The architecture is composed of 9 nodes interconnected to each other through a 3x3 mesh-based Network-on-Chip. The central node of the architecture hosts a RISC processor. This node acts as master of the platform, taking care of the data and task scheduling. The surrounding nodes host a reconfigurable engine and do the actual processing. The system was prototyped on an Altera FPGA device and RTL simulations of the architecture were carried out to ensure the correct functionality of the system. The platform was designed to process streaming applications. As an example of these applications, a finite impulse response filter was mapped on the system. Simulation results showed a speed-up of 6.8x over the same FIR filter implemented on a COFFEE RISC core, while requiring a 20% less resources of similar architecture composed by a homogeneous mesh of COFFEE RISC cores