Verification of Identity and Syntax Check of Verilog and LEF Files

The Verilog and LEF files are units of the digital design flow [1][2]. They are being developed in different stages. Before the development of the LEF file, the Verilog file passes through numerous steps during which partial losses of information are possible. The identity check allows to make sure that during the flow the information has not been lost. The syntax accuracy of the Verilog and LEF files is checked as well. nbspnbspnbspnbspnbspnbspnbspnbspnbspnbspnbsp The scripting language Perl is selected for the program. The language is flexible to work with text files [3]. nbspnbspnbspnbspnbspnbspnbspnbspnbspnbspnbsp The method developed in the present paper is substantial as the application of integrated circuits today is actual in different scientific, technical and many other spheres which gradually finds wider application bringing about large demand

Formal reasoning with Verilog HDL

Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are dened, and properties about synchronization and mutual exclusion algorithms are proved.peer-reviewe

Correct hardware compilation with Verilog HDL

Hardware description languages usually include features which do not have a direct hardware interpretation. Recently, synthesis algorithms allowing some of these features to be compiled into circuits have been developed and implemented. Using a formal semantics of Verilog based on Relational Duration Calculus, we give a number of algebraic laws which Verilog programs obey, using which, we then prove the correctness of a hardware compilation procedure.peer-reviewe

Towards An Automated Approach to Hardware/Software Decomposition

We propose in this paper an algebraic approach to hard-ware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog. Through this, we confirm successful verification for the correctness of the partitioning process by an algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.Singapore-MIT Alliance (SMA

Putting Operational Techniques to the Test: A Syntactic Theory for Behavioral Verilog

AbstractWe present a syntactic theory for the behavioral subset of the Verilog Hardware Description Language. Due to the complexity of the language, the construction of this theory represents a serious test of the suitability of syntactic operational techniques for reasoning about industrial languages. Overall, we have found that these techniques are rather robust but with a few caveats. Our theory formalizes the simulation cycle explicitly, exposes a number of ambiguities and inconsistencies in the language reference manual (LRM), and is the most accurate known description of this subset of Verilog, with respect to the LRM. The syntactic theory has been used to automatically derive a simulator for Verilog

Relational Semantics of Non-Deterministic Dataflow

We recast dataflow in a modern categorical light using profunctors as a generalization of relations. The well known causal anomalies associated with relational semantics of indeterminate dataflow are avoided, but still we preservemuch of the intuitions of a relational model. The development fits with the view of categories of models for concurrency and the general treatment of bisimulation they provide. In particular it fits with the recent categorical formulation of feedback using traced monoidal categories. The payoffs are: (1) explicit relations to existing models and semantics, especially theusual axioms of monotone IO automata are read off from the definition of profunctors, (2) a new definition of bisimulation for dataflow, the proof of the congruence of which benefits from the preservation properties associated with open maps and (3) a treatment of higher-order dataflow as a biproduct,essentially by following the geometry of interaction programme

Synchronous Digital Circuits as Functional Programs

Functional programming techniques have been used to describe synchronous digital circuits since the early 1980s and have proven successful at describing certain types of designs. Here we survey the systems and formal underpinnings that constitute this tradition. We situate these techniques with respect to other formal methods for hardware design and discuss the work yet to be done

Iodine: Verifying Constant-Time Execution of Hardware

To be secure, cryptographic algorithms crucially rely on the underlying hardware to avoid inadvertent leakage of secrets through timing side channels. Unfortunately, such timing channels are ubiquitous in modern hardware, due to its labyrinthine fast-paths and optimizations. A promising way to avoid timing vulnerabilities is to devise --- and verify --- conditions under which a hardware design is free of timing variability, i.e., executes in constant-time. In this paper, we present Iodine: a clock precise, constant-time approach to eliminating timing side channels in hardware. Iodine succeeds in verifying various open source hardware designs in seconds and with little developer effort. Iodine also discovered two constant-time violations: one in a floating-point unit and another one in an RSA encryption module