Verification of Identity and Syntax Check of Verilog and LEF Files

Abstract

The Verilog and LEF files are units of the digital design flow [1][2]. They are being developed in different stages. Before the development of the LEF file, the Verilog file passes through numerous steps during which partial losses of information are possible. The identity check allows to make sure that during the flow the information has not been lost. The syntax accuracy of the Verilog and LEF files is checked as well. nbspnbspnbspnbspnbspnbspnbspnbspnbspnbspnbsp The scripting language Perl is selected for the program. The language is flexible to work with text files [3]. nbspnbspnbspnbspnbspnbspnbspnbspnbspnbspnbsp The method developed in the present paper is substantial as the application of integrated circuits today is actual in different scientific, technical and many other spheres which gradually finds wider application bringing about large demand