Analysis on the Possibility of RISC-V Adoption

As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change. Since its release in 2010, RISC-V has begun to erode the industry aversion to ISA innovation. Established on the principals of the Reduced Instruction Set Computer (RISC), and as an open source ISA, RISC-V offers many benefits over popular ISAs like Intel’s x86 and Arm Holding’s Advanced RISC Machine (ARM). In this literature review I evaluate the literature discussing: What makes changing Instruction Set Architectures difficultWhy might the industry choose to implement RISC-V When researching this topic I visited the IEEE (Institute of Electrical and Electronics Engineers), INSPEC (Engineering Village), and ACM (Association for Computing Machinery) Digital Library databases. I used the search terms, “RISC-V”, “Instruction Set Architecture”, “RISC-V” AND “x86”, and “RISC-V” AND “Instruction Set Architecture”. This literature review evaluates 10 papers on implementation of RISC-V. As this paper was intended to cover recent developments in the field, publication dates were limited to from 2015 to present

RISC-V Processor for IOT Applications

RISC-V is a recently introduced instruction-set architecture (ISA) that offers innovative advantages, including low power consumption, affordability, and scalability. Utilizing an open, non-proprietary Instruction Set Architecture (ISA) enables the creation of on-the-fly design of soft error countermeasures at the microarchitecture level. This may significantly enhance the resilience of Application Specific Standard Products (ASSP) and FPGA implementations. This paper offers a quick overview of the RISC-V architecture. This paper presents a plan to create and execute a 32-bit single-cycle RISC-V processor using Verilog HDL in the Vivado software

Efficient Cryptography on the RISC-V Architecture

RISC-V is a promising free and open-source instruction set architecture. Most of the instruction set has been standardized and several hardware implementations are commercially available. In this paper we highlight features of RISC-V that are interesting for optimizing implementations of cryptographic primitives. We provide the first optimized assembly implementations of table-based AES, bitsliced AES, ChaCha, and the Keccak-$f$[1600] permutation for the RV32I instruction set. With respect to public-key cryptography, we study the performance of arbitrary-precision integer arithmetic without a carry flag. We then estimate the improvement that can be gained by several RISC-V extensions. These performance studies also serve to aid design choices for future RISC-V extensions and implementations

ECC Memory for Fault Tolerant RISC-V Processors

Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. However, so far only very little concepts and implementations for fault tolerant RISC-V processors are existing. This inhibits the use of RISC-V for safety-critical applications (as in the automotive domain) or within radiation environments (as in the aerospace domain). This work enhances the existing implementations Rocket and BOOM with a generic Error Correction Code (ECC) protected memory as a first step towards fault tolerance. The impact of the ECC additions on performance and resource utilization are discussed

OTTER Vector Extension

This paper offers an implementation of a subset of the RISC-V \u27V\u27 Vector Extension , v0.7.x. The RISC-V \u27V\u27 Vector Extension is the proposed vector instruction set for RISC-V open-source architecture. Vectors are inherently data-parallel, allowing for significant performance increases. Vectors have applications in fields such as cryptography, graphics, and machine learning. A vector processing unit was added to Cal Poly\u27s RISC-V multi-cycle architecture, known as the OTTER. Computationally intensive programs running on the OTTER Vector Extension ran over three times faster when compared to the baseline multi-cycle implementation. Memory intensive applications saw similar performance increases

Superscalar RISC-V Processor with SIMD Vector Extension

With the increasing number of digital products in the market, the need for robust and highly configurable processors rises. The demand is convened by the stable and extensible open-sourced RISC-V instruction set architecture. RISC-V processors are becoming popular in many fields of applications and research. This thesis presents a dual-issue superscalar RISC-V processor design with dynamic execution. The proposed design employs the global sharing scheme for branch prediction and Tomasulo algorithm for out-of-order execution. The processor is capable of speculative execution with five checkpoints. Data flow in the instruction dispatch and commit stages is optimized to achieve higher instruction throughput. The superscalar processor is extended with a customized vector instruction set of single-instruction-multiple-data computations to specifically improve the performance on machine learning tasks. According to the definition of the proposed vector instruction set, the scratchpad memory and element-wise arithmetic units are implemented in the vector co-processor. Different test programs are evaluated on the fully-tested superscalar processor. Compared to the reference work, the proposed design improves 18.9% on average instruction throughput and 4.92% on average prediction hit rate, with 16.9% higher operating clock frequency synthesized on the Intel Arria 10 FPGA board. The forward propagation of a convolution neural network model is evaluated by the standalone superscalar processor and the integration of the vector co-processor. The vector program with software-level optimizations achieves 9.53× improvement on instruction throughput and 10.18× improvement on real-time throughput. Moreover, the integration also provides 2.22× energy efficiency compared with the superscalar processor along

Framework Pengembangan Hardware dan Pembahasan Instruction Set Architecture RISC-V dan Implementasi dengan PCM5102.

Kondisi teknologi saat ini memerlukan sebuah Instruction Set Architecture (ISA) yang bersifat modular dan memiliki konsumsi daya yang lebih rendah, dan Reduced Instruction Set V (RISC-V) merupakan salah satu ISA yang dirancang untuk memenuhi kebutuhan tersebut. Jika dibandingkan dengan Complex Instruction Set Computer (CISC), RISC-V memiliki keuntungan dalam efisiensi dan tingkat modularitas. Pada makalah survei sebelumnya yang di lakukan oleh A. Dörflinger et al dan R. Höller et al belum melakukan pengujian terhadap perangkat RISC-V yang dijual pasaran dan hanya berupa soft core Field Programable Gate Array (FPGA), oleh karena itu salah satu perangkat keras RISC-V, yaitu ESP32C3 dibahas, diuji, dan dibandingkan dengan ESP32WROOM menggunakan aplikasi Dhrystone serta diukur arusnya. Berdasarkan pengujian tersebut, ESP32C3 memiliki performa 3,2 kali lebih baik daripada ESP32WROOM yang dijalankan pada mode single core. Sedangkan untuk impelementasi ESP32C3 dengan chip DAC PCM5102 berhasil menghasilkan gelombang sinus 492.971 Hz yang memiliki tegangan 960 mV puncak ke puncak dan menghasilkan distorsi kurang dari -40 dB.Current technological conditions require an Instruction Set Architecture (ISA) that is modular and has lower power consumption, and Reduced Instruction Set V (RISC-V) is one of the ISAs designed to meet these needs. When compared to a Complex Instruction Set Computer (CISC), RISC-V has advantages in efficiency and modularity. In the previous survey paper conducted by A. Dörflinger et al and R. Höller et al, they had not tested RISC-V devices that were sold on the market and were only in the form of Field Programmable Gate Array (FPGA) soft cores, therefore one of the hardware devices RISC-V, namely the ESP32C3 was discussed, tested, and compared with the ESP32WROOM using the Dhrystone application and the current was measured. Based on these tests, ESP32C3 has 3.2 times better performance than ESP32WROOM which is run in single core mode. Meanwhile, the implementation of the ESP32C3 with the PCM5102 DAC chip succeeded in producing a 492.971 Hz sine wave which has a peak-to-peak voltage of 960 mV and produces less than -40 dB distortion.

RISC-V Processor Model

V rámci snahy o minimalizaci spotřeby a plochy na čipu dochází k vývoji procesorů s aplikačně specifickou instrukční sadou. Dochází tak k vytváření nových instrukčních sad, které však často bývají tajné. Proti tomuto trendu stojí instrukční sada RISC-V, vyvinutá Kalifornskou univerzitou v Berkeley, která je plně otevřena. V této diplomové práci se pozornost věnuje analýze instrukční sady RISC-V a jazyků Chisel a CodAL, které slouží k popisu instrukčních sad a počítačových architektur. Jádrem práce je implementace modelu základní instrukční sady RISC-V a rozšíření pro dělení, násobení a 64-bitový adresový prostor a dále implementace modelu časování založeného na mikroarchitektuře Rocket Core. To vše v jazyce CodAL. Modely jsou dále využity ke generování překladače jazyka C a RTL reprezentace procesoru ve vývojovém prostředí Codasip Studio. Získaný překladač je porovnán s překladačem dostupným od tvůrců instrukční sady a výsledky použity k optimalizaci instrukční sady. RTL je syntetyzováno na FPGA Artix 7 a srovnáno s výsledky syntézy Rocket Core.The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.