Electrocardiogram (ECG/EKG) using FPGA

FPGAs (Field Programmable Gate Arrays) are finding wide acceptance in medical systems for their ability for rapid prototyping of a concept that requires hardware/software co-design, for performing custom processing in parallel at high data rates and be programmed in the field after manufacturing. Based on the market demand, the FPGA design can be changed and no new hardware needs to be purchased as was the case with ASICs (Application Specific Integrated Circuit) and CPLDs (Complex Programmable Logic Device). Medical companies can now move over to FPGAs saving cost and delivering highly-efficient upgradable systems. ECG (Electrocardiogram) is considered to be a must have feature for a medical diagnostic imaging system. This project attempts at implementing ECG heart-rate computation in an FPGA. This project gave me exposure to hardware engineering, learning about the low level chips like Atmel UC3A3256 micro-controller on an Atmel EVK1105 board which is used as a simulator for generating the ECG signal, the operational amplifiers for amplifying and level-shifting the ECG signal, the A/D converter chip for analog to digital conversion of the ECG signal, the internal workings of FPGA, how different hardware components communicate with each other on the system and finally some signal processing to calculate the heart rate value from the ECG signal

Digital Complex Correlator for a C-band Polarimetry survey

The international Galactic Emission Mapping project aims to map and characterize the polarization field of the Milky Way. In Portugal it will cartograph the C-band sky polarized emission of the Northern Hemisphere and provide templates for map calibration and foreground control of microwave space probes like ESA Planck Surveyor mission. The receiver system is equipped with a novel receiver with a full digital back-end using an Altera Field Programmable Gate Array, having a very favorable cost/performance relation. This new digital backend comprises a base-band complex cross-correlator outputting the four Stokes parameters of the incoming polarized radiation. In this document we describe the design and implementation of the complex correlator using COTS components and a processing FPGA, detailing the method applied in the several algorithm stages and suitable for large sky area surveys.Comment: 15 pages, 10 figures; submitted to Experimental Astronomy, Springe

Implementation Aspects of a Transmitted-Reference UWB Receiver

In this paper, we discuss the design issues of an ultra wide band (UWB) receiver targeting a single-chip CMOS implementation for low data-rate applications like ad hoc wireless sensor networks. A non-coherent transmitted reference (TR) receiver is chosen because of its small complexity compared to other architectures. After a brief recapitulation of the UWB fundamentals and a short discussion on the major differences between coherent and non-coherent receivers, we discuss issues, challenges and possible design solutions. Several simulation results obtained by means of a behavioral model are presented, together with an analysis of the trade-off between performance and complexity in an integrated circuit implementation

Stellar intensity interferometry: Experimental steps toward long-baseline observations

Experiments are in progress to prepare for intensity interferometry with arrays of air Cherenkov telescopes. At the Bonneville Seabase site, near Salt Lake City, a testbed observatory has been set up with two 3-m air Cherenkov telescopes on a 23-m baseline. Cameras are being constructed, with control electronics for either off- or online analysis of the data. At the Lund Observatory (Sweden), in Technion (Israel) and at the University of Utah (USA), laboratory intensity interferometers simulating stellar observations have been set up and experiments are in progress, using various analog and digital correlators, reaching 1.4 ns time resolution, to analyze signals from pairs of laboratory telescopes.Comment: 12 pages, 3 figur

Hardware Design for Quadrature Phase Detection Algorithm in ECVT

Core processing for calculating phase andamplitude of the detected signal was built on FPGA (Field-Programmable Gate-Array) platform. Phase shift demodulationalgorithm employs IP core provided by Xilinx FPGA. Directdigital synthesizer (DDS), multiplier, accumulator, and CORDIC(coordinate rotation digital computer) modules were used asexcitation-reference signal generator, signal multiplication,accumulation, and conversion to polar coordinate in order toconduct trigonometric operation respectively. Hardware designwas emulated on MATLAB-Xilinx System Generator to observeits performance. Phase detection range 0-114.58o and meanabsolute error 0.58o have been achieved. Data processing ratesolely at digital signal stage was approximately 100data/s suitablefor 32-channel ECVT (electrical capacitance volumetomography) system