Exploitation of Digital Filters to Advance the Single-Phase T/4 Delay PLL System

With the development of digital signal processing technologies, control and monitoring of power electronics conversion systems have been evolving to become fully digital. As the basic element in the design and analysis phases of digital controllers or filters, a number of unit delays (z-1) have been employed, e.g., in a cascaded structure. Practically, the number of unit delays is designed as an integer, which is related to the sampling frequency as well as the ac signal fundamental frequency (e.g., 50 Hz). More common, the sampling frequency is fixed during operation for simplicity and design. Hence, any disturbance in the ac signal will violate this design rule and it can become a major challenge for digital controllers. To deal with the above issue, this paper first exploits a virtual unit delay (zv-1) to emulate the variable sampling behavior in practical digital signal processors with a fixed sampling rate. This exploitation is demonstrated on a T/4 Delay Phase Locked Loop (PLL) system for a single-phase grid-connected inverter. The T/4 Delay PLL requires to cascade 50 unit delays when implemented (for a 50-Hz system with 10 kHz sampling frequency). Furthermore, digital frequency adaptive comb filters are adopted to enhance the performance of the T/4 Delay PLL when the grid suffers from harmonics. Experimental results have confirmed the effectiveness of the digital filters for advanced control systems

Influence of the ICFF decoupling technique on the stability of the current control loop of a grid-tied VSC

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The control scheme of grid-tied converters is often implemented in the dq-frame due to simplicity of design. However, with this transformation, there exists an inherent cross-coupling term between the d-and q-channels which is often compensated for by using a feed-forward term in the current-control loop. It is shown, by applying the generalized Nyquist criterion (GNC) to the dq-frame ac impedance of the converter, that the inclusion of this decoupling term, in fact, degrades the stability of the controller when increasing the bandwidth of the synchronous reference frame phase-locked loop (SRF-PLL). Harware-in-the-loop (HIL) experiments are also conducted and verify these results.Peer ReviewedPostprint (author's final draft

Harnessing high-dimensional hyperentanglement through a biphoton frequency comb

Quantum entanglement is a fundamental resource for secure information processing and communications, where hyperentanglement or high-dimensional entanglement has been separately proposed towards high data capacity and error resilience. The continuous-variable nature of the energy-time entanglement makes it an ideal candidate for efficient high-dimensional coding with minimal limitations. Here we demonstrate the first simultaneous high-dimensional hyperentanglement using a biphoton frequency comb to harness the full potential in both energy and time domain. The long-postulated Hong-Ou-Mandel quantum revival is exhibited, with up to 19 time-bins, 96.5% visibilities. We further witness the high-dimensional energy-time entanglement through Franson revivals, which is observed periodically at integer time-bins, with 97.8% visibility. This qudit state is observed to simultaneously violate the generalized Bell inequality by up to 10.95 deviations while observing recurrent Clauser-Horne-Shimony-Holt S-parameters up to 2.76. Our biphoton frequency comb provides a platform in photon-efficient quantum communications towards the ultimate channel capacity through energy-time-polarization high-dimensional encoding

Limitations of PLL simulation: hidden oscillations in MatLab and SPICE

Nonlinear analysis of the phase-locked loop (PLL) based circuits is a challenging task, thus in modern engineering literature simplified mathematical models and simulation are widely used for their study. In this work the limitations of numerical approach is discussed and it is shown that, e.g. hidden oscillations may not be found by simulation. Corresponding examples in SPICE and MatLab, which may lead to wrong conclusions concerning the operability of PLL-based circuits, are presented

Dynamics estimation and generalized tuning of stationary frame current controller for grid-tied power converters

The integration of AC-DC power converters to manage the connection of generation to the grid has increased exponentially over the last years. PV or wind generation plants are one of the main applications showing this trend. High power converters are increasingly installed for integrating the renewables in a larger scale. The control design for these converters becomes more challenging due to the reduced control bandwidth and increased complexity in the grid connection filter. A generalized and optimized control tuning approach for converters becomes more favored. This paper proposes an algorithm for estimating the dynamic performance of the stationary frame current controllers, and based on it a generalized and optimized tuning approach is developed. The experience-based specifications of the tuning inputs are not necessary through the tuning approach. Simulation and experimental results in different scenarios are shown to evaluate the proposal.Peer ReviewedPostprint (published version

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Creating high dimensional time-bin entanglement using mode-locked lasers

We present a new scheme to generate high dimensional entanglement between two photonic systems. The idea is based on parametric down conversion with a sequence of pump pulses generated by a mode-locked laser. We prove experimentally the feasibility of this scheme by performing a Franson-type Bell test using a 2-way interferometer with path-length difference equal to the distance between 2 pump pulses. With this experiment, we can demonstrate entanglement for a two-photon state of at least dimension D=11. Finally, we propose a feasible experiment to show a Fabry-Perot like effect for a high dimensional two-photon state.Comment: 5 pages, 5 figure