The FMCAD 2016 Graduate Student Forum

The FMCAD Student Forum provides a platform for graduate students at any career stage to introduce their research to the wider Formal Methods community, and solicit feedback.In 2016, the event took place in Mountain View, California, as integral part of the FMCAD conference. Ten students were invited to give a short talk and present a poster illustrating their work. The presentations covered a broad range of topics in the field of verification and synthesis, including automated reasoning, model checking of hardware, software, as well as hybrid systems, verification and synthesis of networks, and application of artificial intelligence techniques to circuit design

Texas ScholarWorks: 14-15 Annual Report

UT Librarie

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Computer Aided Verification

The open access two-volume set LNCS 12224 and 12225 constitutes the refereed proceedings of the 32st International Conference on Computer Aided Verification, CAV 2020, held in Los Angeles, CA, USA, in July 2020.* The 43 full papers presented together with 18 tool papers and 4 case studies, were carefully reviewed and selected from 240 submissions. The papers were organized in the following topical sections: Part I: AI verification; blockchain and Security; Concurrency; hardware verification and decision procedures; and hybrid and dynamic systems. Part II: model checking; software verification; stochastic systems; and synthesis. *The conference was held virtually due to the COVID-19 pandemic

A primordial, mathematical, logical and computable, demonstration (proof) of the family of conjectures known as Goldbach´s

licencia de Creative Commons Reconocimiento-NoComercial-SinObraDerivada 4.0 Internacional.In this document, by means of a novel system model and first order topological, algebraic and geometrical free-­‐context formal language (NT-­‐FS&L), first, we describe a new signature for a set of the natural numbers that is rooted in an intensional inductive de-­‐embedding process of both, the tensorial identities of the known as “natural numbers”, and the abstract framework of theirs locus-­‐positional based symbolic representations. Additionally, we describe that NT-­‐FS&L is able to: i.-­‐ Embed the De Morgan´s Laws and the FOL-­‐Peano´s Arithmetic Axiomatic. ii.-­‐ Provide new points of view and perspectives about the succession, precede and addition operations and of their abstract, topological, algebraic, analytic geometrical, computational and cognitive, formal representations. Second, by means of the inductive apparatus of NT-­‐FS&L, we proof that the family of conjectures known as Glodbach’s holds entailment and truth when the reasoning starts from the consistent and finitary axiomatic system herein describedWe wish to thank the Organic Chemistry Institute of the Spanish National Research Council (IQOG/CSIC) for its operative and technical support to the Pedro Noheda Research Group (PNRG). We also thank the Institute for Physical and Information Technologies (ITETI/CSIC) of the Spanish National Research Council for their hospitality. We also thank for their long years of dedicated and kind support Dr. Juan Martínez Armesto (VATC/CSIC), Belén Cabrero Suárez (IQOG/CSIC, Administration), Mar Caso Neira (IQOG/CENQUIOR/CSIC, Library) and David Herrero Ruíz (PNRG/IQOG/CSIC). We wish to thank to Bernabé-­‐Pajares´s brothers (Dr. Manuel Bernabé-­‐Pajares, IQOG/CSIC Structural Chemistry & Biochemistry; Magnetic Nuclear Resonance and Dr. Alberto Bernabé Pajares (Greek Philology and Indo-­‐European Linguistics/UCM), for their kind attention during numerous and kind discussions about space, time, imaging and representation of knowledge, language, transcription mistakes, myths and humans always holding us familiar illusion and passion for knowledge and intellectual progress. We wish to thank Dr. Carlos Cativiela Marín (ISQCH/UNIZAR) for his encouragement and for kind listening and attention. We wish to thank Miguel Lorca Melton for his encouragement and professional point of view as Patent Attorney. Last but not least, our gratitude to Nati, María and Jaime for the time borrowed from a loving husband and father. Finally, we apologize to many who have not been mentioned today, but to whom we are grateful. Finally, let us point out that we specially apologize to many who have been mentioned herein for any possible misunderstanding regarding the sense and intension of their philosophic, scientific and/or technical hard work and milestone ideas; we hope that at least Goldbach, Euler and Feymann do not belong to this last human´s collectivity.Peer reviewe

Automated Approaches for Program Verification and Repair

Formal methods techniques, such as verification, analysis, and synthesis,allow programmers to prove properties of their programs, or automatically derive programs from specifications. Making such techniques usable requires care: they must provide useful debugging information, be scalable, and enable automation. This dissertation presents automated analysis and synthesis techniques to ease the debugging of modular verification systems and allow easy access to constraint solvers from functional code. Further, it introduces machine learning based techniques to improve the scalability of off-the-shelf syntax-guided synthesis solvers and techniques to reduce the burden of network administrators writing and analyzing firewalls. We describe the design and implementationof a symbolic execution engine, G2, for non-strict functional languages such as Haskell. We extend G2 to both debug and automate the process of modular verification, and give Haskell programmers easy access to constraints solvers via a library named G2Q. Modular verifiers, such as LiquidHaskell, Dafny, and ESC/Java,allow programmers to write and prove specifications of their code. When a modular verifier fails to verify a program, it is not necessarily because of an actual bug in the program. This is because when verifying a function f, modular verifiers consider only the specification of a called function g, not the actual definition of g. Thus, a modular verifier may fail to prove a true specification of f if the specification of g is too weak. We present a technique, counterfactual symbolic execution, to aid in the debugging of modular verification failures. The approach uses symbolic execution to find concrete counterexamples, in the case of an actual inconsistency between a program and a specification; and abstract counterexamples, in the case that a function specification is too weak. Further, a counterexample-guided inductive synthesis (CEGIS) loop based technique is introduced to fully automate the process of modular verification, by using found counterexamples to automatically infer needed function specifications. The counterfactual symbolic execution and automated specification inference techniques are implemented in G2, and evaluated on existing LiquidHaskell errors and programs. We also leveraged G2 to build a library, G2Q, which allows writing constraint solving problemsdirectly as Haskell code. Users of G2Q can embed specially marked Haskell constraints (Boolean expressions) into their normal Haskell code, while marking some of the variables in the constraint as symbolic. Then, at runtime, G2Q automatically derives values for the symbolic variables that satisfy the constraint, and returns those values to the outside code. Unlike other constraint solving solutions, such as directly calling an SMT solver, G2Q uses symbolic execution to unroll recursive function definitions, and guarantees that the use of G2Q constraints will preserve type correctness. We further consider the problem of synthesizing functions viaa class of tools known as syntax-guided synthesis (SyGuS) solvers. We introduce a machine learning based technique to preprocess SyGuS problems, and reduce the space that the solver must search for a solution in. We demonstrate that the technique speeds up an existing SyGuS solver, CVC4, on a set of SyGuS solver benchmarks. Finally, we describe techniques to ease analysis and repair of firewalls.Firewalls are widely deployed to manage network security. However, firewall systems provide only a primitive interface, in which the specification is given as an ordered list of rules. This makes it hard to manually track and maintain the behavior of a firewall. We introduce a formal semantics for iptables firewall rules via a translation to first-order logic with uninterpreted functions and linear integer arithmetic, which allows encoding of firewalls into a decidable logic. We then describe techniques to automate the analysis and repair of firewalls using SMT solvers, based on user provided specifications of the desired behavior. We evaluate this approach with real world case studies collected from StackOverflow users