A language for the integration of web sources

This is an electronic version of the paper presented at the IADIS International Conference WWW / INTERNET 2006, held in Murcia on 2006This paper presents a language for the creation of data sources in mediation systems through navigation in web sites. The general idea of the language is to “thread together,” so to speak, existing systems that parse and analyze single web pages into a navigation procedure spanning several pages of a web site, pages from different web sites, or web pages and other data repositories

An implementation of the forth language on Heath H-89 microcomputer, 1981

The primary intent of this thesis is to discuss how to use the Forth language on the Heath H-89 microcomputer. Forth is a programming language with a small, but fast-growing, enthusiastic user community. Forth was invented by Mr. Charles H. Moore in 1973.Forth is a very compact language which only needs a small memory storage. It is also a threaded language which starts with a few fundamental subroutines written in machine languag

MWTerm: a macintosh based multiple-window unix workstation

MWTerm is a terminal emulator that runs on an Apple Macintosh computer. It provides a multiple window interface in which each window maps to a independent process on the host computer. It is designed to run in conjunction with a cooperating program on the host computer, under the Unix operating system. This paper describes the ideas behind the user interface presented by MWTerm. The implementation of both the Macintosh and the Unix ends is described. A discussion of the lessons learned and future enhancements is provided

Verification of Smart Contracts using the Interactive Theorem Prover Agda

The goal of this thesis is to verify smart contracts in Blockchain. In particular, we focus on smart contracts in Bitcoin and Solidity. In order to specify the correctness of smart contracts, we use weakest preconditions. For this, we develop a model of smart contracts in the interactive theorem prover and dependent type programming language Agda and prove the correctness of smart contracts in it. In the context of Bitcoin, our verification of Bitcoin scripts consists of non-conditional and conditional scripts. For Solidity, we refer to programs using object-oriented features of Solidity, such as calling of other contracts, full recursion, and the use of gas in order to guarantee termination while having a Turing-complete language. We have developed a simulator for Solidity-style smart contracts. As a main example, we executed a reentrancy attack in our model. We have verified smart contracts in Bitcoin and Solidity using weakest precondition in Agda. Furthermore, Agda, combined with the fact that it is a theorem prover and programming language, allows the writing of verified programs, where the verification takes place in the same language in which the program is written, avoiding the problem of translation from one language to another (with possible translation mistakes)

A principled approach to REPL interpreters

Read-eval-print-loops (REPLs) allow programmers to test out snippets of code, explore APIs, or even incrementally construct code, and get immediate feedback on their actions. However, even though many languages provide a REPL, the relation between the language as is and what is accepted at the REPL prompt is not always well-defined. Furthermore, implementing a REPL for new languages, such as DSLs, may incur significant language engineering cost. In this paper we survey the domain of REPLs and investigate the (formal) principles underlying REPLs. We identify and define the class of sequential languages, which admit a sound REPL implementation based on a definitional interpreter, and present design guidelines for extending existing language implementations to support REPL-style interfaces (including computational notebooks). The obtained REPLs can then be generically turned into an exploring interpreter, to allow exploration of the user’s interaction.The approach is illustrated using three case studies, based on MiniJava, QL (a DSL for questionnaires), and eFLINT (a DSL for normative rules). We expect sequential languages, and the consequent design principles, to be stepping stones towards a better understanding of the essence of REPLs.</p

Second-Generation Stack Computer Architecture

The Independent Studies program closed in 2016. This thesis was one of 25 accepted by Library for long-term preservation and presentation in UWSpace.It is commonly held in current computer architecture literature that stack-based computers were entirely superseded by the combination of pipelined, integrated microprocessors and improved compilers. While correct, the literature omits a second, new generation of stack computers that emerged at the same time. In this thesis, I develop historical, qualitative, and quantitative distinctions between the first and second generations of stack computers. I present a rebuttal of the main arguments against stack computers and show that they are not applicable to those of the second generation. I also present an example of a small, modern stack computer and compare it to the MIPS architecture. The results show that second-generation stack computers have much better performance for deeply nested or recursive code, but are correspondingly worse for iterative code. The results also show that even though the stack computer’s zero-operand instruction format only moderately increases the code density, it significantly reduces instruction memory bandwidth

An asynchronous forth microprocessor.

Ping-Ki Tsang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.Includes bibliographical references (leaves 87-95).Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation and Aims --- p.1Chapter 1.2 --- Contributions --- p.3Chapter 1.3 --- Overview of the Thesis --- p.4Chapter 2 --- Asynchronous Logic g --- p.6Chapter 2.1 --- Motivation --- p.6Chapter 2.2 --- Timing Models --- p.9Chapter 2.2.1 --- Fundamental-Mode Model --- p.9Chapter 2.2.2 --- Delay-Insensitive Model --- p.10Chapter 2.2.3 --- QDI and Speed-Independent Models --- p.11Chapter 2.3 --- Asynchronous Signalling Protocols --- p.12Chapter 2.3.1 --- 2-phase Handshaking Protocol --- p.12Chapter 2.3.2 --- 4-phase Handshaking Protocol --- p.13Chapter 2.4 --- Data Representations --- p.14Chapter 2.4.1 --- Dual Rail Coded Data --- p.15Chapter 2.4.2 --- Bundled Data --- p.15Chapter 2.5 --- Previous Asynchronous Processors --- p.16Chapter 2.6 --- Summary --- p.20Chapter 3 --- The MSL16 Architecture --- p.21Chapter 3.1 --- RISC Machines --- p.21Chapter 3.2 --- Stack Machines --- p.23Chapter 3.3 --- Forth and its Applications --- p.24Chapter 3.4 --- MSL16 --- p.26Chapter 3.4.1 --- Architecture --- p.28Chapter 3.4.2 --- Instruction Set --- p.30Chapter 3.4.3 --- The Datapath --- p.32Chapter 3.4.4 --- Interrupts and Exceptions --- p.33Chapter 3.4.5 --- Implementing Forth primitives --- p.34Chapter 3.4.6 --- Code Density Estimation --- p.34Chapter 3.5 --- Summary --- p.35Chapter 4 --- Design Methodology --- p.37Chapter 4.1 --- Basic Notation --- p.38Chapter 4.2 --- Specification of MSL16A --- p.39Chapter 4.3 --- Decomposition into Concurrent Processes --- p.41Chapter 4.4 --- Separation of Control and Datapath --- p.45Chapter 4.5 --- Handshaking Expansion --- p.45Chapter 4.5.1 --- 4-Phase Handshaking Protocol --- p.46Chapter 4.6 --- Production-rule Expansion --- p.47Chapter 4.7 --- Summary --- p.48Chapter 5 --- Implementation --- p.49Chapter 5.1 --- C-element --- p.49Chapter 5.2 --- Mutual Exclusion Elements --- p.51Chapter 5.3 --- Caltech Asynchronous Synthesis Tools --- p.53Chapter 5.4 --- Stack Design --- p.54Chapter 5.4.1 --- Eager Stack Control --- p.55Chapter 5.4.2 --- Lazy Stack Control --- p.56Chapter 5.4.3 --- Eager/Lazy Stack Datapath --- p.53Chapter 5.4.4 --- Pointer Stack Control --- p.61Chapter 5.4.5 --- Pointer Stack Datapath --- p.62Chapter 5.5 --- ALU Design --- p.62Chapter 5.5.1 --- The Addition Operation --- p.63Chapter 5.5.2 --- Zero-Checker --- p.64Chapter 5.6 --- Memory Interface and Tri-state Buffers --- p.64Chapter 5.7 --- MSL16A --- p.65Chapter 5.8 --- Summary --- p.66Chapter 6 --- Results --- p.67Chapter 6.1 --- FPGA based implementation of MSL16 --- p.67Chapter 6.2 --- MSL16A --- p.69Chapter 6.2.1 --- A Comparison of 3 Stack Designs --- p.69Chapter 6.2.2 --- Evaluation of the ALU --- p.73Chapter 6.2.3 --- Evaluation of MSL16A --- p.74Chapter 6.3 --- Summary --- p.81Chapter 7 --- Conclusions --- p.83Chapter 7.1 --- Future Work --- p.85Bibliography --- p.87Publications --- p.9