4,909 research outputs found

    Bank market power and financial reporting quality

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    Joining the debate on the banking sector’s impact on the real economy, this study examines the impact of banks’ market power on local businesses’ financial reporting quality. Based on the market power hypothesis and the information-based hypothesis, we propose four ways the banking market could affect the financial reporting quality. The proposed mechanisms suggest that borrowers and bank lenders face increased market power by implementing different earnings management and monitoring practices. Our documentary evidence suggests that since the banking market deregulation, restrictions on inter- and intra-state banking and branching have been removed, with banks gaining more power and the market becoming more consolidated. Using a large sample of U.S. listed firms from 1995-2019, we find a favourable impact of bank market power on corporate financial reporting quality, primarily driven by heightened monitoring by banks with greater market power, supporting the monitoring-stringent conjecture. In addition, this positive relationship is more pronounced among firms heavily reliant on local banks. Our results are robust to a rich set of tests, such as using alternative measurements for financial reporting quality and bank market power, including macroeconomic factors, and considering drastic changes in the bank market structure. We also address the endogeneity concerns and test the robustness of our key findings in a loan syndication setting. Our research suggests that facing increased bank market concentration and power, firms must pay additional attention to their financial reporting, which is widely used to access external finance

    Climate Change and Critical Agrarian Studies

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    Climate change is perhaps the greatest threat to humanity today and plays out as a cruel engine of myriad forms of injustice, violence and destruction. The effects of climate change from human-made emissions of greenhouse gases are devastating and accelerating; yet are uncertain and uneven both in terms of geography and socio-economic impacts. Emerging from the dynamics of capitalism since the industrial revolution — as well as industrialisation under state-led socialism — the consequences of climate change are especially profound for the countryside and its inhabitants. The book interrogates the narratives and strategies that frame climate change and examines the institutionalised responses in agrarian settings, highlighting what exclusions and inclusions result. It explores how different people — in relation to class and other co-constituted axes of social difference such as gender, race, ethnicity, age and occupation — are affected by climate change, as well as the climate adaptation and mitigation responses being implemented in rural areas. The book in turn explores how climate change – and the responses to it - affect processes of social differentiation, trajectories of accumulation and in turn agrarian politics. Finally, the book examines what strategies are required to confront climate change, and the underlying political-economic dynamics that cause it, reflecting on what this means for agrarian struggles across the world. The 26 chapters in this volume explore how the relationship between capitalism and climate change plays out in the rural world and, in particular, the way agrarian struggles connect with the huge challenge of climate change. Through a huge variety of case studies alongside more conceptual chapters, the book makes the often-missing connection between climate change and critical agrarian studies. The book argues that making the connection between climate and agrarian justice is crucial

    Transnational Education: Risking ‘recolonisation’

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    LLaMA-Reviewer: Advancing Code Review Automation with Large Language Models through Parameter-Efficient Fine-Tuning (Practical Experience Report)

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    The automation of code review activities, a long-standing pursuit in software engineering, has been primarily addressed by numerous domain-specific pre-trained models. Despite their success, these models frequently demand extensive resources for pre-training from scratch. In contrast, Large Language Models (LLMs) provide an intriguing alternative, given their remarkable capabilities when supplemented with domain-specific knowledge. However, their potential for automating code review tasks remains largely unexplored. In response to this research gap, we present LLaMA-Reviewer, an innovative framework that leverages the capabilities of LLaMA, a popular LLM, in the realm of code review. Mindful of resource constraints, this framework employs parameter-efficient fine-tuning (PEFT) methods, delivering high performance while using less than 1% of trainable parameters. An extensive evaluation of LLaMA-Reviewer is conducted on two diverse, publicly available datasets. Notably, even with the smallest LLaMA base model consisting of 6.7B parameters and a limited number of tuning epochs, LLaMA-Reviewer equals the performance of existing code-review-focused models. The ablation experiments provide insights into the influence of various fine-tuning process components, including input representation, instruction tuning, and different PEFT methods. To foster continuous progress in this field, the code and all PEFT-weight plugins have been made open-source.Comment: Accepted to the 34th IEEE International Symposium on Software Reliability Engineering (ISSRE 2023

    Potential of machine learning/Artificial Intelligence (ML/AI) for verifying configurations of 5G multi Radio Access Technology (RAT) base station

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    Abstract. The enhancements in mobile networks from 1G to 5G have greatly increased data transmission reliability and speed. However, concerns with 5G must be addressed. As system performance and reliability improve, ML and AI integration in products and services become more common. The integration teams in cellular network equipment creation test devices from beginning to end to ensure hardware and software parts function correctly. Radio unit integration is typically the first integration phase, where the radio is tested independently without additional network components like the BBU and UE. 5G architecture and the technology that it is using are explained further. The architecture defined by 3GPP for 5G differs from previous generations, using Network Functions (NFs) instead of network entities. This service-based architecture offers NF reusability to reduce costs and modularity, allowing for the best vendor options for customer radio products. 5G introduced the O-RAN concept to decompose the RAN architecture, allowing for increased speed, flexibility, and innovation. NG-RAN provided this solution to speed up the development and implementation process of 5G. The O-RAN concept aims to improve the efficiency of RAN by breaking it down into components, allowing for more agility and customization. The four protocols, the eCPRI interface, and the functionalities of fronthaul that NGRAN follows are expressed further. Additionally, the significance of NR is described with an explanation of its benefits. Some benefits are high data rates, lower latency, improved spectral efficiency, increased network flexibility, and improved energy efficiency. The timeline for 5G development is provided along with different 3GPP releases. Stand-alone and non-stand-alone architecture is integral while developing the 5G architecture; hence, it is also defined with illustrations. The two frequency bands that NR utilizes, FR1 and FR2, are expressed further. FR1 is a sub-6 GHz frequency band. It contains frequencies of low and high values; on the other hand, FR2 contains frequencies above 6GHz, comprising high frequencies. FR2 is commonly known as the mmWave band. Data collection for implementing the ML approaches is expressed that contains the test setup, data collection, data description, and data visualization part of the thesis work. The Test PC runs tests, executes test cases using test libraries, and collects data from various logs to analyze the system’s performance. The logs contain information about the test results, which can be used to identify issues and evaluate the system’s performance. The data collection part describes that the data was initially present in JSON files and extracted from there. The extraction took place using the Python code script and was then fed into an Excel sheet for further analysis. The data description explains the parameters that are taken while training the models. Jupyter notebook has been used for visualizing the data, and the visualization is carried out with the help of graphs. Moreover, the ML techniques used for analyzing the data are described. In total, three methods are used here. All the techniques come under the category of supervised learning. The explained models are random forest, XG Boost, and LSTM. These three models form the basis of ML techniques applied in the thesis. The results and discussion section explains the outcomes of the ML models and discusses how the thesis will be used in the future. The results include the parameters that are considered to apply the ML models to them. SINR, noise power, rxPower, and RSSI are the metrics that are being monitored. These parameters have variance, which is essential in evaluating the quality of the product test setup, the quality of the software being tested, and the state of the test environment. The discussion section of the thesis explains why the following parameters are taken, which ML model is most appropriate for the data being analyzed, and what the next steps are in implementation

    Q-Learning applied to games: a reward focused study

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    Dissertação de mestrado integrado em Informatics EngineeringQ-Learning is one of the most popular reinforcement learning algorithms. It can solve different complex problems with interesting tasks where decisions have to be made, all the while using the same algorithm with no interfer ence from the developer about specific strategies. This is achieved by processing a reward received after each decision is made. In order to evaluate the performance of Q-Learning on different problems, video games prove to be a great asset for testing purposes, as each game has its own unique mechanics and some kind of objective that needs to be learned. Furthermore, the results from testing different algorithms on the same conditions can be easily compared. This thesis presents a study on Q-Learning, from its origins and how it operates, showcasing various state of the art techniques used to improve the algorithm and detailing the procedures that have become standard when training Q-Learning agents to play video games for the Atari 2600. Our implementation of the algorithm following the same techniques and procedures is ran on different video games. The training performance is compared to the one obtained in articles that trained on the same games and attained state of the art performance. Additionally, we explored crafting new reward schemes modifying game default rewards. Various custom rewards were created and combined to evaluate how they affect performance. During these tests, we found that the use of rewards that inform about both good and bad behaviour led to better performance, as opposed to rewards that only inform about good behaviour, which is done by default in some games. It was also found that the use of more game specific rewards could attain better results, but these also required a more careful analysis of each game, not being easily transferable into other games. As a more general approach, we tested reward changes that could incentivize exploration for games that were harder to navigate, and thus harder to learn from. We found that not only did these changes improve exploration, but they also improved the performance obtained after some parameter tuning. These algorithms are designed to teach the agent to accumulate rewards. But how does this relate to game score? To assess this question, we present some preliminary experiments showing the relationship between the evolution of reward accumulation and game score.Q-Learning é um dos algoritmos mais populares de aprendizagem por reforço. Este consegue resolver vários problemas complexos que tenham tarefas interessantes e decisões que devem ser tomadas. Para todos os problemas, o mesmo algoritmo é utilizado sem haver interferência por parte do desenvolvedor sobre estratégias específicas que existam. Isto tudo é alcançado processando uma recompensa que é recebida após tomar cada decisão. Para avaliar o desempenho de Q-Learning em problemas diferentes, os jogos eletrónicos trazem grandes vantagens para fins de teste, pois cada jogo tem as suas próprias regras e algum tipo de objetivo que precisa de ser compreendido. Além disso, os resultados dos testes usando diferentes algoritmos nas mesmas condições podem ser facilmente comparados. Esta tese apresenta um estudo sobre Q-Learning, explicando as suas origens e como funciona, apresentando várias técnicas de estado da arte usadas para melhorar o algoritmo e detalhando os procedimentos padrão usados para treinar agentes de Q-Learning a jogar jogos eletrónicos da Atari 2600. A nossa implementação do algoritmo seguindo as mesmas técnicas e procedimentos é executada em diferentes jogos eletrónicos. O desempenho durante o treino é comparado ao desempenho obtido em artigos que treinaram nos mesmos jogos e atingiram resultados de estado da arte. Além disso, exploramos a criação de novos esquemas de recompensas, modificando as recompensas usadas nos jogos por defeito. Várias recompensas novas foram criadas e combinadas para avaliar como afetam o desempenho do agente. Durante estes testes, observamos que o uso de recompensas que informam tanto sobre o bom como o mau comportamento levaram a um melhor desempenho, ao contrário de recompensas que apenas informam sobre o bom comportamento, que acontece em alguns jogos usando as recompensas por defeito. Também se observou que o uso de recompensas mais específicas para um jogo pode levar a melhores resultados, mas essas recompensas também exigem uma análise mais cuidadosa de cada jogo e não são facilmente transferíveis para outros jogos. Numa abordagem mais geral, testamos mudanças de recompensas que poderiam incentivar a exploração em jogos mais difíceis de navegar e, portanto, mais difíceis de aprender. Observamos que estas mudanças não só melhoraram a exploração, como também o desempenho obtido após alguns ajustes de parâmetros. Estes algoritmos têm como objetivo ensinar o agente a acumular recompensas. Como é que isto está relacionado com a pontuação obtida no jogo? Para abordar esta questão, apresentamos alguns testes preliminares que mostram a relação entre a evolução da acumulação de recompensas e da pontuação no jogo

    ACiS: smart switches with application-level acceleration

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    Network performance has contributed fundamentally to the growth of supercomputing over the past decades. In parallel, High Performance Computing (HPC) peak performance has depended, first, on ever faster/denser CPUs, and then, just on increasing density alone. As operating frequency, and now feature size, have levelled off, two new approaches are becoming central to achieving higher net performance: configurability and integration. Configurability enables hardware to map to the application, as well as vice versa. Integration enables system components that have generally been single function-e.g., a network to transport data—to have additional functionality, e.g., also to operate on that data. More generally, integration enables compute-everywhere: not just in CPU and accelerator, but also in network and, more specifically, the communication switches. In this thesis, we propose four novel methods of enhancing HPC performance through Advanced Computing in the Switch (ACiS). More specifically, we propose various flexible and application-aware accelerators that can be embedded into or attached to existing communication switches to improve the performance and scalability of HPC and Machine Learning (ML) applications. We follow a modular design discipline through introducing composable plugins to successively add ACiS capabilities. In the first work, we propose an inline accelerator to communication switches for user-definable collective operations. MPI collective operations can often be performance killers in HPC applications; we seek to solve this bottleneck by offloading them to reconfigurable hardware within the switch itself. We also introduce a novel mechanism that enables the hardware to support MPI communicators of arbitrary shape and that is scalable to very large systems. In the second work, we propose a look-aside accelerator for communication switches that is capable of processing packets at line-rate. Functions requiring loops and states are addressed in this method. The proposed in-switch accelerator is based on a RISC-V compatible Coarse Grained Reconfigurable Arrays (CGRAs). To facilitate usability, we have developed a framework to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator. In the third work, we extend ACiS to support fused collectives and the combining of collectives with map operations. We observe that there is an opportunity of fusing communication (collectives) with computation. Since the computation can vary for different applications, ACiS support should be programmable in this method. In the fourth work, we propose that switches with ACiS support can control and manage the execution of applications, i.e., that the switch be an active device with decision-making capabilities. Switches have a central view of the network; they can collect telemetry information and monitor application behavior and then use this information for control, decision-making, and coordination of nodes. We evaluate the feasibility of ACiS through extensive RTL-based simulation as well as deployment in an open-access cloud infrastructure. Using this simulation framework, when considering a Graph Convolutional Network (GCN) application as a case study, a speedup of on average 3.4x across five real-world datasets is achieved on 24 nodes compared to a CPU cluster without ACiS capabilities

    Tiny Machine Learning Environment: Enabling Intelligence on Constrained Devices

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    Running machine learning algorithms (ML) on constrained devices at the extreme edge of the network is problematic due to the computational overhead of ML algorithms, available resources on the embedded platform, and application budget (i.e., real-time requirements, power constraints, etc.). This required the development of specific solutions and development tools for what is now referred to as TinyML. In this dissertation, we focus on improving the deployment and performance of TinyML applications, taking into consideration the aforementioned challenges, especially memory requirements. This dissertation contributed to the construction of the Edge Learning Machine environment (ELM), a platform-independent open-source framework that provides three main TinyML services, namely shallow ML, self-supervised ML, and binary deep learning on constrained devices. In this context, this work includes the following steps, which are reflected in the thesis structure. First, we present the performance analysis of state-of-the-art shallow ML algorithms including dense neural networks, implemented on mainstream microcontrollers. The comprehensive analysis in terms of algorithms, hardware platforms, datasets, preprocessing techniques, and configurations shows similar performance results compared to a desktop machine and highlights the impact of these factors on overall performance. Second, despite the assumption that TinyML only permits models inference provided by the scarcity of resources, we have gone a step further and enabled self-supervised on-device training on microcontrollers and tiny IoT devices by developing the Autonomous Edge Pipeline (AEP) system. AEP achieves comparable accuracy compared to the typical TinyML paradigm, i.e., models trained on resource-abundant devices and then deployed on microcontrollers. Next, we present the development of a memory allocation strategy for convolutional neural networks (CNNs) layers, that optimizes memory requirements. This approach reduces the memory footprint without affecting accuracy nor latency. Moreover, e-skin systems share the main requirements of the TinyML fields: enabling intelligence with low memory, low power consumption, and low latency. Therefore, we designed an efficient Tiny CNN architecture for e-skin applications. The architecture leverages the memory allocation strategy presented earlier and provides better performance than existing solutions. A major contribution of the thesis is given by CBin-NN, a library of functions for implementing extremely efficient binary neural networks on constrained devices. The library outperforms state of the art NN deployment solutions by drastically reducing memory footprint and inference latency. All the solutions proposed in this thesis have been implemented on representative devices and tested in relevant applications, of which results are reported and discussed. The ELM framework is open source, and this work is clearly becoming a useful, versatile toolkit for the IoT and TinyML research and development community

    Tools for efficient Deep Learning

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    In the era of Deep Learning (DL), there is a fast-growing demand for building and deploying Deep Neural Networks (DNNs) on various platforms. This thesis proposes five tools to address the challenges for designing DNNs that are efficient in time, in resources and in power consumption. We first present Aegis and SPGC to address the challenges in improving the memory efficiency of DL training and inference. Aegis makes mixed precision training (MPT) stabler by layer-wise gradient scaling. Empirical experiments show that Aegis can improve MPT accuracy by at most 4\%. SPGC focuses on structured pruning: replacing standard convolution with group convolution (GConv) to avoid irregular sparsity. SPGC formulates GConv pruning as a channel permutation problem and proposes a novel heuristic polynomial-time algorithm. Common DNNs pruned by SPGC have maximally 1\% higher accuracy than prior work. This thesis also addresses the challenges lying in the gap between DNN descriptions and executables by Polygeist for software and POLSCA for hardware. Many novel techniques, e.g. statement splitting and memory partitioning, are explored and used to expand polyhedral optimisation. Polygeist can speed up software execution in sequential and parallel by 2.53 and 9.47 times on Polybench/C. POLSCA achieves 1.5 times speedup over hardware designs directly generated from high-level synthesis on Polybench/C. Moreover, this thesis presents Deacon, a framework that generates FPGA-based DNN accelerators of streaming architectures with advanced pipelining techniques to address the challenges from heterogeneous convolution and residual connections. Deacon provides fine-grained pipelining, graph-level optimisation, and heuristic exploration by graph colouring. Compared with prior designs, Deacon shows resource/power consumption efficiency improvement of 1.2x/3.5x for MobileNets and 1.0x/2.8x for SqueezeNets. All these tools are open source, some of which have already gained public engagement. We believe they can make efficient deep learning applications easier to build and deploy.Open Acces
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