Property Verification within a Process Algebra Framework

We present a methodology for the automatic verification of concurrent systems by using the constraint-based modelling style available within the Circal process algebra: the behaviour of a process may be constrained simply by composing it with another process which represents the constraints. A property of a system is characterized by a Circal process, which can be either a translation of a formula described using the temporal logic SAUB or the specification of a well-known model that satisfies the property. This methodology is automated by the Circal System and has been applied to the verification of communication protocols

Modelling Digital Logic in SDL

The specification of digital logic in SDL (Specification and Description Language) is investigated. A specification approach is proposed for multi-level descriptions of hardware behaviour and structure. The modelling method exploits features introduced in SDL-92. The approach also deals with the specification, analysis and simulation of timing aspects at any level in the specification of digital logic

Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks

Asynchronous circuits have several advantages for security applications, in particular their good resistance to attacks. In this paper, we report on experiments with modeling, at various abstraction levels, a patented asynchronous circuit for detecting physical attacks, such as cutting wires or producing short-circuits.Comment: In Proceedings MARS 2020, arXiv:2004.1240

FPGA urban traffic control simulation and evaluation platform

Mestrado em Engenharia Electrónica e TelecomunicaçõesThe study and development towards Urban Traffic Management and Control (UTMC) Systems have not solely or recently gained extreme importance only due to obvious issues such as traffic safety improvement, traffic congestion control and avoidance but also due to other underlying factors such as urban transportation efficiency, urban traffic originated air pollution and future concepts as are autonomous vehicle systems, which are presently taking shape. Generally speaking urban traffic simulations occur in a software environment, which comes to hinder the progress taken towards the actual implementation of UTMC systems. The reason to why such happens is based on the fact that urban traffic controllers are usually implemented and executed on hardware platforms, therefore software based models don‟t support an actual implementation directly. In this study we explore a novel approach to urban traffic simulation, aimed to eliminate the timeframe and work-distance between the UTMC system‟s design and an eventual implementation, where a Field Programmable Gate Array (FPGA) is used to execute a simulation model of an urban traffic network. Since the resource to FPGAs implies a hardware based execution, the resulting implementation of each traffic management and control element can be considered not only as having a close matched behavior to a real world implementation but also as an actual prototype. From the simulation viewpoint the use of FPGA‟s holds the prospect of being able to hold execution speeds many times faster than software based simulations as FPGA designs are able to execute a large number of parallel processes. This study shows that an Urban Traffic Control Simulation and Test Platform is possible by implementing a relatively simple urban network model in a low end FPGA. This result implies that with further time and resource investments a rather complex system can be developed which can handle large scale and complex UTMC systems with the promise of shortening the work distance between the concept and a real world running implementation

Simulating vehicular traffic flows using the Circal System.

Modern civil engineers have big problems on their hands; more cars use our road networks every year, leading to ever increasing congestion. Knowing how to change a road network to relieve congestion without spending millions of pounds doing so is a tricky business. Traffic simulators can go some way to helping the engineers know how flows will alter with changes in the network. Such changes could be a new road, or even a simple modification to a signalized junction's phasing. Unfortunately, accurate simulators typically available to engineers are slow to execute, especially if the network being simulated is the size of a city. Real-time simulations are available, running on parallel platforms, but these are costly.This paper discusses the initial research into traffic simulation on programmable logic devices (PLDs). This promises simulations speeds which are faster than real time, but at a fraction of the cost of simulators based on parallel architecture. Rather that trying to map road networks directly onto the PLDs, we have used a hardware description language, XCircal, to model our hardware components. Each component corresponds to a part of a road network, such as a section of road or a one-lane to two-lane splitter. Using XCircal, full junctions can be modelled without touching the hardware. Results of a simulation are included, and these demonstrate that basic junction behaviour can be replicated in hardware

An exercise in the automatic verification of asynchronous designs

This paper illustrates the practical application of an automatic formal verification technique to circuit designs of realistic complexity. The Circal System is presented and a number of asynchronous hardware modules are described and formally verified using it. Asynchronous logic is generally considered hard to design and analyse, and this serves as an appropriate demonstration of the features of a formal description and verification system

Simulating vehicular traffic flows using the Circal System.

Modern civil engineers have big problems on their hands; more cars use our road networks every year, leading to ever increasing congestion. Knowing how to change a road network to relieve congestion without spending millions of pounds doing so is a tricky business. Traffic simulators can go some way to helping the engineers know how flows will alter with changes in the network. Such changes could be a new road, or even a simple modification to a signalized junction's phasing. Unfortunately, accurate simulators typically available to engineers are slow to execute, especially if the network being simulated is the size of a city. Real-time simulations are available, running on parallel platforms, but these are costly.This paper discusses the initial research into traffic simulation on programmable logic devices (PLDs). This promises simulations speeds which are faster than real time, but at a fraction of the cost of simulators based on parallel architecture. Rather that trying to map road networks directly onto the PLDs, we have used a hardware description language, XCircal, to model our hardware components. Each component corresponds to a part of a road network, such as a section of road or a one-lane to two-lane splitter. Using XCircal, full junctions can be modelled without touching the hardware. Results of a simulation are included, and these demonstrate that basic junction behaviour can be replicated in hardware