Animatronic Monarch Butterfly: Mechanical System

This report describes the design, manufacturing, and design verification of an interactive animatronic monarch butterfly created by a team of mechanical and computer engineering students for the Girl Scouts of California\u27s Central Coast. The purpose of the project is to engage Girl Scouts in learning about monarch butterflies and provide hands-on experience in robotics and STEM. The report covers design changes, manufacturing processes, and assembly of various components, including the butterfly body, wings, legs, and electronic housing. The software and electronics used in the project are also briefly discussed, as the computer engineering team was responsible for the software and electronics. Design verification was conducted through computerized simulations and physical testing, ensuring that the specifications were met. Finally, next steps, future testing, and goals for the next team that takes over this project are outlined

Aerospace Senior Design Project, In-Orbit Manufacturing Process of Electronic Enclosures

This report presents the final design of A-MOD\u27s groundbreaking in-orbit electronic enclosure manufacturing device. The detailed design, encompassing analysis, specifications, and component specifics, showcases the feasibility of the proposed system. With objectives met, the report navigates through the concept of operations, validation and verification processes, critical design of mechanical and electrical components, software integration, performance specifications, and a comprehensive risk assessment. A-MOD\u27s design revolutionizes space technology by proposing a device capable of manufacturing electronic enclosures in orbit, reducing costs and optimizing resources. Thorough validation and verification procedures ensure the system\u27s adherence to stringent requirements, covering precision, quality, thermal resilience, and power efficiency, providing confidence in the robustness of the design. The critical design section highlights the meticulous mechanical design, detailing overall dimensions, manufacturing head specifics, and material storage mechanisms supported by CAD models and simulations. Although secondary in focus, the electrical design section outlines essential aspects, emphasizing wiring, off-the-shelf electrical components, and microcontroller usage, contributing to the system\u27s overall efficiency. The performance specifications provide crucial metrics for evaluating efficiency in terms of mass, time, power consumption, and production quantity, with an enclosure test case serving as a benchmark for raw material optimization. The detailed risk assessment identifies potential challenges, emphasizing preventive actions and continuous testing and research, instilling confidence in the system\u27s reliability. In essence, A-MOD\u27s report offers a deep dive into groundbreaking space technology, presenting a design and a vision for the future of in-orbit manufacturing. The comprehensive insights and innovative solutions detailed in this report make it a must-read for space technology enthusiasts, researchers, and professionals seeking cutting-edge advancements in space manufacturing capabilities. The four most significant benefits of A-MOD\u27s design to society and potential customers are its cost efficiency, rapid prototyping capabilities, reduced environmental impact, and enhanced space exploration capabilities. These advantages collectively position the in-orbit electronic enclosure manufacturing device as a transformative technology with broad implications for the space industry and beyond

Functional Verification of Power Electronic Systems

This project is the final work of the degree in Industrial Electronics and Automatic Engineering. It has global concepts of electronics but it focuses in power electronic systems. There is a need for reliable testing systems to ensure the good functionality of power electronic systems. The constant evolution of this products requires the development of new testing techniques. This project aims to develop a new testing system to accomplish the functional verification of a new power electronic system manufactured on a company that is in the power electronic sector . This test system consists on two test bed platforms, one to test the control part of the systems and the other one to test their functionality. A software to perform the test is also designed. Finally, the testing protocol is presented. This design is validated and then implemented on a buck converter and an inverter that are manufactured at the company. The results show that the test system is reliable and is capable of testing the functional verification of the two power electronic system successfully. In summary, this design can be introduced in the power electronic production process to test the two products ensuring their reliability in the market

IEEE Standard 1500 Compliance Verification for Embedded Cores

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standar

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs)