The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

Abstract

Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs)