Lachesis: a testsuite for Linux based real-time systems

none2Testing is a key step in software development cycle. Error and bug fixing costs can easily exceed development costs without a full and comprehensive test on the system. First efforts to introduce real-time features in the Linux kernel are now more than ten years old. Nevertheless, no comprehensive testsuites is able to assess the functionality or the conformance to the real-time operating systems standards of the Linux kernel and of real-time nanokernels that rely on it. In this paper we propose Lachesis, an automated testsuite derived from the LTP (Linux Test Project) real-time tests. Lachesis main goals are: to provide extensive and comprehensive testing of real-time Linux features; to provide a set of functional, regression, performance and stress test, either developing or porting them from other testsuites; to design and experiment a series of build tests; to minimize development time for new tests; to make the testsuite extensible and portable. Lachesis can be used to test Linux, PREEMPT_RT, RTAI and Xenomai real-time features and performances. It provides some tests for SCHED_DEADLINE patch, too. Lachesis is now under active development: extensions to other real-time systems and more tests are planned to be added in the near future.A. Claudi; A. F. DragoniClaudi, Andrea; Dragoni, Aldo Franc

Algorithmic methods to infer the evolutionary trajectories in cancer progression

The genomic evolution inherent to cancer relates directly to a renewed focus on the voluminous next-generation sequencing data and machine learning for the inference of explanatory models of how the (epi)genomic events are choreographed in cancer initiation and development. However, despite the increasing availability of multiple additional -omics data, this quest has been frustrated by various theoretical and technical hurdles, mostly stemming from the dramatic heterogeneity of the disease. In this paper, we build on our recent work on the 'selective advantage' relation among driver mutations in cancer progression and investigate its applicability to the modeling problem at the population level. Here, we introduce PiCnIc (Pipeline for Cancer Inference), a versatile, modular, and customizable pipeline to extract ensemble-level progression models from cross-sectional sequenced cancer genomes. The pipeline has many translational implications because it combines state-of-the-art techniques for sample stratification, driver selection, identification of fitness-equivalent exclusive alterations, and progression model inference. We demonstrate PiCnIc's ability to reproduce much of the current knowledge on colorectal cancer progression as well as to suggest novel experimentally verifiable hypotheses

Relative timing

Journal ArticleRelative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative timing enables improved performance, area, power and testability in all three cases

Structure and Problem Hardness: Goal Asymmetry and DPLL Proofs in<br> SAT-Based Planning

In Verification and in (optimal) AI Planning, a successful method is to formulate the application as boolean satisfiability (SAT), and solve it with state-of-the-art DPLL-based procedures. There is a lack of understanding of why this works so well. Focussing on the Planning context, we identify a form of problem structure concerned with the symmetrical or asymmetrical nature of the cost of achieving the individual planning goals. We quantify this sort of structure with a simple numeric parameter called AsymRatio, ranging between 0 and 1. We run experiments in 10 benchmark domains from the International Planning Competitions since 2000; we show that AsymRatio is a good indicator of SAT solver performance in 8 of these domains. We then examine carefully crafted synthetic planning domains that allow control of the amount of structure, and that are clean enough for a rigorous analysis of the combinatorial search space. The domains are parameterized by size, and by the amount of structure. The CNFs we examine are unsatisfiable, encoding one planning step less than the length of the optimal plan. We prove upper and lower bounds on the size of the best possible DPLL refutations, under different settings of the amount of structure, as a function of size. We also identify the best possible sets of branching variables (backdoors). With minimum AsymRatio, we prove exponential lower bounds, and identify minimal backdoors of size linear in the number of variables. With maximum AsymRatio, we identify logarithmic DPLL refutations (and backdoors), showing a doubly exponential gap between the two structural extreme cases. The reasons for this behavior -- the proof arguments -- illuminate the prototypical patterns of structure causing the empirical behavior observed in the competition benchmarks

Using Rust as a Complement to C for Embedded Systems Software Development

Rust aims to bring safety to low-level programming by using zero-cost ab- stractions. These provide, among other things, guaranteed memory safety and threading without data races. Garbage collected languages have become popular to guarantee safety, but in performance critical, memory limited or real time applications, it is not an ideal solution. Rust is safe and still has manual memory management, with strict rules. This report presents a case study of using the Rust language and associated tooling such as debuggers and IDEs in practise. The study was carried out by porting 5000+ lines of an embedded Linux daemon to Rust. Rust upholds the safety and zero-cost claims. Using Rust has been found to aid in achieving an improved, shorter, more expressive architecture. The learning curve is a bit steep, but productivity has been found to be high once learned. Tooling support is mature, but IDEs are not yet full featured.Programmeringsspråket Rust utvecklas av en grupp som anser att det saknas språk som passar lågnivåutveckling och samtidigt är säkra. Rust har utvärderats genom att översätta 5000+ rader C-kod i ett inbyggt system. Rust levererar säkerhet, är smidigt och är inte resursintensivt

Algorithmic methods to infer the evolutionary trajectories in cancer progression

The genomic evolution inherent to cancer relates directly to a renewed focus on the voluminous next generation sequencing (NGS) data, and machine learning for the inference of explanatory models of how the (epi)genomic events are choreographed in cancer initiation and development. However, despite the increasing availability of multiple additional -omics data, this quest has been frustrated by various theoretical and technical hurdles, mostly stemming from the dramatic heterogeneity of the disease. In this paper, we build on our recent works on "selective advantage" relation among driver mutations in cancer progression and investigate its applicability to the modeling problem at the population level. Here, we introduce PiCnIc (Pipeline for Cancer Inference), a versatile, modular and customizable pipeline to extract ensemble-level progression models from cross-sectional sequenced cancer genomes. The pipeline has many translational implications as it combines state-of-the-art techniques for sample stratification, driver selection, identification of fitness-equivalent exclusive alterations and progression model inference. We demonstrate PiCnIc's ability to reproduce much of the current knowledge on colorectal cancer progression, as well as to suggest novel experimentally verifiable hypotheses

PORTING OF FREERTOS ON A PYTHON VIRTUAL MACHINE FOR EMBEDDED AND IOT DEVICES

The fourth industrial revolution, The Industry 4.0, puts emphasis on the need of “Smart” and “Connected” objects through the use of services provided by Internet of Things, cyber-physical systems and cloud computing to optimize the cost, development time and remote connectivity. Development of highly scalable and flexible IoT applications is the need of time. These solutions require connectivity, less development time, time-to-market and at the same time offers a high performance and great reliability. Zerynth, a small company, provides its full stack for IoT solutions. Zerynth Virtual Machine is the core component among other components in stack which allow the programmers to code in python or hybrid C/Python coding with multithreaded Real Time OS with negligible memory footprint. The Python layer, Application Layer, is totally agnostic of underlying RTOS and hardware abstraction layer. This layered software architecture of Zerynth VM makes it totally compatible with new Industry 4.0 standard. The Hardware abstraction layer, VHAL, abstracts the hardware features of supported MCU and its peripherals while RTOS layer, VOSAL, uses the features of underlying Real Time OS. Zerynth VM can be ported with different Real Time OS and various hardware platforms depending upon the application’s cost, features and other relevant parameters. Configuring Kinetis MCU (MK64FN1M0VDC12) with existing VM became the first objective of my thesis. This configuration covers from scratch the clock, boot loading and peripheral support. Since previous version of Zerynth VM had a support of only Chibi2 OS which has certain dependency on the hardware layer underneath so this became another objective to separate the Chibi2 OS from VHAL layer for total independence. Finally, Porting of FreeRTOS on Zerynth VM with Hexiwear MCU as target board could a make a room for another RTOS hence enhancing the features and support of currently available VM. This thesis report describes all porting steps, procedures and testing methodologies starting from configuring a new hardware platform Hexiwear to FreeRTOS porting on Zerynth V

Relative timing

Journal ArticleAbstract-Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3x in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated