VHDL Models with Usage of the LFSR_PCKG Package

LFSRs (Linear Feedback Shift Registers) are very often used in the BIST (Built-In Self-Test) methodology. Implementation of the LFSRs to the design or application of digital system, which supports BIST techniques or which only uses these LFSRs, can be done by VHDL language. This paper presents VHDL models of the devices and subroutines (e.g. test pattern generators, signature analysers). Models are based on LFSR structures with usage of the LFSR_PCKG package described in the (Kovalsky and Vlcek, 2001), which can be used in the applications supporting BIST techniques. Devices are described as behavioural and structural models. These models and descriptions can be used e.g. in the (Kovalsky, 2001). The LFSR_PCKG was modified and new approach is presented. Naturally, there are presented some synthesis conclusions of the VHDL models and applications in this paper

Design a Low Power Built in Self-Test (BIST) Architecture for Fast Multiplier and Optimize in Terms of Real Time Functionality

Aiming low power during testing, Maypresent a methodology for derivingBIST Architecture forfast Multipliers. In my propose Researchseveral design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BISTArchitecture for the derived multipliers is achieved by: (i) IntroducingTest Pattern Generators (ii) Properly assigning the TPGsoutputs to the multiplier inputs and(iii) Significantly reducing the test vector length. In this work, I have implemented 4bit * 4bit Multiplier with many test pattern generators (TPG) alternative. A BIST TPG Architecture was use of 6 bit counter. I have calculated operation speed, time delay, area, power consumption for Design. Reductionof power dissipationachieved byproperly assigning the TPG output to the multiplier input,significantly reducing the test set length, suitableTPG built of a6-bit counter DOI: 10.17762/ijritcc2321-8169.150317

Method for Testing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. Specifically, the FPGA under test may be configured to act as an iterative logic array wherein a first group of programmable logic blocks are configured as test pattern generators, output response analyzers and helper cells, and a second group of programmable logic blocks are configured as blocks under test. The blocks under test are then repeatedly reconfigured in order to completely test each block under test in all possible modes of operation. The first and second groups of programmable logic blocks are then repeatedly rearranged so that all the programmable logic blocks are established as blocks under test at least once. Following the rearrangement, the repeated reconfiguration of the blocks under test is performed once again

Method of Testing and Diagnosing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes establishing a first group of programmable logic blocks as test pattern generators or output response analyzers and a second group of programmable logic blocks as blocks under test. This is followed by generating test patterns and comparing outputs of two blocks under test with one output response analyzer. Next is the combining of results of a plurality of output response analyzers utilizing an iterative comparator in order to produce a pass/fail indication. The method also includes the step of reconfiguring each block under test so that each block under test is tested in all possible modes of operation. Further, there follows the step of reversing programming of the groups of programmable logic blocks so that each programmable logic block is configured at least once as a block under test

Method for Testing Field Programmable Gate Arrays

A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. This is followed by the steps of initiating the built-in self-test, generating test patterns with the programmable logic blocks and analyzing a resulting response to produce a pass/fail indication with the programmable logic blocks. More specifically, the configuring step includes establishing a first group of programmable logic blocks as test pattern generators and output response analyzers and a second group of programmable logic blocks as blocks under test. The blocks under test are then repeatedly recongifured in order to completely test each block under test in all possible modes of operation. The programming of the first and second groups of programmable logic blocks is then reversed and the testing of each new block under test is then completed

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Designing an efficient test pattern generator using input reduction with linear operations

Advances in fabrication technology have resulted in more complicated systems, being used in ever increasing numbers of applications. The large increase in transistor counts versus the number of pins on the chip has made VLSI testing much harder than ever before. Denser integrated circuits chips increase the required test cases enormously for comprehensive testing of a chip. This results in expensive test cost and long test time. In this thesis, an improved method for on-chip test pattern generation is proposed. It generates a complete test set more efficiently by using input reduction with linear operations. Input reduction for pseudo-exhaustive test pattern generation based on compatible and inverse-compatible relationships between inputs has been proposed in the past. This work extends the concept by using linear combinations of inputs to generate other inputs as a means for further input reduction. Results are presented showing the improvements that can be obtained.Electrical and Computer Engineerin

Baseband processor for IEEE 802.11a standard with embedded BIST

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

On applying the set covering model to reseeding

The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits