REDUCING POWER DURING MANUFACTURING TEST USING DIFFERENT ARCHITECTURES

Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test. In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We group the control bits together into one or more control chains. To address the extra pin(s) required to shift data into the control chain(s) and significant post processing in the first architecture, we explored a second architecture. The second architecture stitches the control bits into the chains they control as EECBs (embedded enable capture bits) in between the segments. This allows an ATPG software tool to automatically generate the appropriate EECB values for each pattern to maintain the fault coverage. This also works in the presence of an on-chip decompressor. The last architecture focuses primarily on the self-test of a device in a 3D stacked IC when an existing FPGA in the stack can be programmed as a tester. We show that the energy expended during test is significantly less than would be required using low power patterns fed by an on-chip decompressor for the same very short scan chains

Consequences of local and global chromatin mechanics to adaption and genome stability in the budding yeast Saccharomyces cerevisiae

Le génome de la levure de boulanger Saccharomyces cerevisiae a évolué à partir d'un ancêtre chez lequel une profonde décompaction du génome s'est produite à la suite de la perte de la méthylation de la lysine 9 de l'histone H3, il y a environ 300 millions d'années. Il a été proposé que cette décompaction du génome a entraîné une capacité accrue des levures à évoluer par des mécanismes impliquant des taux de recombinaison méiotique et de mutation exceptionnellement élevés. La capacité à évoluer accrue qui en résulte pourrait avoir permis des adaptations uniques, qui en ont fait un eucaryote modèle idéal et un outil biotechnologique. Dans cette thèse, je présenterai deux exemples de la façon dont les adaptations locales et globales du génome se reflètent dans les changements des propriétés mécaniques de la chromatine qui, à leur tour, indiquent un phénomène de séparation de phase causée par les modifications post-traductionnelles des histones et des changements dans les taux d'échange des histones. Dans un premier manuscrit, je présente des preuves d'un mécanisme par lequel la relocalisation du locus INO1, gène actif répondant à la déplétion en inositol, du nucléoplasme vers l'enveloppe nucléaire, augmente la vitesse d'adaptation et la robustesse métabolique aux ressources fluctuantes, en augmentant le transport des ARNm vers le cytosol et leur traduction. La répartition d'INO1 vers l'enveloppe nucléaire est déterminée par une augmentation locale des taux d'échange d'histones, ce qui entraîne sa séparation de phase du nucléoplasme en une phase de faible densité plus proche de la périphérie nucléaire. J'ai quantifié les propriétés mécaniques de la chromatine du locus du gène dans les états réprimé et actif en analysant le déplacement de 128 sites LacO fusionnés au gène liant LacI-GFP en calculant diffèrent paramètres tel que la constante de ressort effective et le rayons de confinement du locus. De plus, j'ai mesuré l'amplitude et le taux d'expansion en fonction du temps du réseau LacO et j'ai observé une diminution significative du locus à l'état actif, ce qui est cohérent avec le comportement de ressort entropique de la chromatine décompactée. J'ai montré que les séquences d'éléments en cis dans le promoteur du locus, essentielles à la séparation de phase, sont des sites de liaison pour les complexes de remodelage de la chromatine effectuant l'acétylation des histones. Ces modifications de la chromatine entraînent une augmentation des taux d'échanges des sous-unités des complexes d'histones, et une séparation de phase locale de la chromatine. Enfin, je présente l’analyse de simulations in silico qui montrent que la séparation de phase locale de la chromatine peut être prédite à partir d'un modèle de formation/disruption des interactions multivalentes protéine-protéine et protéine-ADN qui entraîne une diminution de la dynamique de l'ADN. Ces résultats suggèrent un mécanisme général permettant de contrôler la formation rapide des domaines de la chromatine, bien que les processus spécifiques contribuant à la diminution de la dynamique de l'ADN restent à étudier. Dans un second manuscrit, je décris comment nous avons induit la « retro-évolution » de la levure en réintroduisant la méthylation de la lysine 9 de l'histone H3 par l'expression de deux gènes de la levure Schizosaccaromyces pombe Spswi6 et Spclr4. Le mutant résultant présente une augmentation de la compaction de la chromatine, ce qui entraîne une réduction remarquable des taux de mutation et de recombinaison. Ces résultats suggèrent que la perte de la méthylation de la lysine 9 de l'histone H3 pourrait avoir augmenté la capacité à l'évoluer. La stabilité inhabituelle du génome conférée par ces mutations pourrait être utile pour l'ingénierie métabolique de S. cerevisiae, dans laquelle il est difficile de maintenir des gènes exogènes intégrés pour les applications de nombreux processus biotechnologiques courants tels que la production de vin, de bière, de pain et de biocarburants. Ces résultats soulignent l'influence des propriétés physiques d'un génome sur son architecture et sa fonction globales.The genome of the budding yeast Saccharomyces cerevisiae evolved from an ancestor in which a profound genome decompaction occurred as the result of the loss of histone H3 lysine 9 methylation, approximately 300 million years ago. This decompaction may have resulted in an increased capacity of yeasts to evolve by mechanisms that include unusually high meiotic recombination and mutation rates. Resultant increased evolvability may have enabled unique adaptations, which have made it an ideal model eukaryote and biotechnological tool. In this thesis I will present two examples of how local and global genome adaptations are reflected in changes in the mechanical properties of chromatin. In a first manuscript, I present evidence for a mechanism by which partitioning of the active inositol depletion-responsive gene locus INO1 from nucleoplasm to the nuclear envelope increases the speed of adaptation and metabolic robustness to fluctuating resources, by increasing mRNA transport to the cytosol and their translation. Partitioning of INO1 to the nuclear envelope is driven by a local increase in histone exchange rates, resulting in its phase separation from the nucleoplasm into a low-density phase closer to the nuclear periphery. I quantified the mechanical properties of the gene locus chromatin in repressed and active states by monitoring mean-squared displacement of an array of 128 LacO sites fused to the gene binding LacI-GFP and calculating effective spring constants and radii of confinement of the array. Furthermore, I measured amplitude and rate of time-dependent expansion of the LacO array, and observed a significant decrease for the active-state locus which is consistent with entropic spring behavior of decompacted chromatin. I showed that cis element sequences in the promoter and upstream of the locus that are essential to phase separation are binding sites for chromatin remodeling complexes that perform histone acetylation among other modifications that result in increased histone complex exchange rates, and consequent local chromatin phase separation. Finally, I present analytical simulations that show that local phase separation of chromatin can be predicted from a model of formation/disruption of multivalent protein-protein and protein-DNA interactions that results in decreased DNA dynamics. These results suggest a general mechanism to control rapid formation of chromatin domains, although the specific processes contributing to the decreased DNA dynamics remain to be investigated. In a second manuscript, I describe how we retro-evolutionarily engineered yeast by reintroducing histone H3 lysine 9 methylation through the expression of two genes from the yeast Schizosaccaromyces pombe Spswi6 and Spclr4. This mutant shows an increase in compaction, resulting in remarkable reduced mutation and recombination rates. These results suggest that loss of histone H3 lysine 9 methylation may have increased evolvability. The unusual genome stability imparted by these mutations could be of value to metabolically engineering S. cerevisiae, in which it is difficult to maintain integrated exogenous genes for applications for many common biotechnological processes such as wine, beer, bread, and biofuels production. These results highlight the influence of the physical properties of a genome on its overall architecture and function

Efficient verification/testing of system-on-chip through fault grading and analog behavioral modeling

textThis dissertation presents several cost-effective production test solutions using fault grading and mixed-signal design verification cases enabled by analog behavioral modeling. Although the latest System-on-Chip (SOC) is getting denser, faster, and more complex, the manufacturing technology is dominated by subtle defects that are introduced by small-scale technology. Thus, SOC requires more mature testing strategies. By performing various types of testing, better quality SoC can be manufactured, but test resources are too limited to accommodate all those tests. To create the most efficient production test flow, any redundant or ineffective tests need to be removed or minimized. Chapter 3 proposes new method of test data volume reduction by combining the nonlinear property of feedback shift register (FSR) and dictionary coding. Instead of using the nonlinear FSR for actual hardware implementation, the expanded test set by nonlinear expansion is used as the one-column test sets and provides big reduction ratio for the test data volume. The experimental results show the combined method reduced the total test data volume and increased the fault coverage. Due to the increased number of test patterns, total test time is increased. Chapter 4 addresses a whole process of functional fault grading. Fault grading has always been a ”desire-to-have” flow because it can bring up significant value for cost saving and yield analysis. However, it is very hard to perform the fault grading on the complex large scale SOC. A commercial tool called Z01X is used as a fault grading platform, and whole fault grading process is coordinated and each detailed execution is performed. Simulation- based functional fault grading identifies the quality of the given functional tests against the static faults and transition delay faults. With the structural tests and functional tests, functional fault grading can indicate the way to achieve the same test coverage by spending minimal test time. Compared to the consumed time and resource for fault grading, the contribution to the test time saving might not be acceptable as very promising, but the fault grading data can be reused for yield analysis and test flow optimization. For the final production testing, confident decisions on the functional test selection can be made based on the fault grading results. Chapter 5 addresses the challenges of Package-on-Package (POP) testing. Because POP devices have pins on both the top and the bottom of the package, the increased test pins require more test channels to detect packaging defects. Boundary scan chain testing is used to detect those continuity defects by relying on leakage current from the power supply. This proposed test scheme does not require direct test channels on the top pins. Based on the counting algorithm, minimal numbers of test cycles are generated, and the test achieved full test coverage for any combinations of pin-to-pin shortage defects on the top pins of the POP package. The experimental results show about 10 times increased leakage current from the shorted defect. Also, it can be expanded to multi-site testing with less test channels for high-volume production. Fault grading is applied within different structural test categories in Chapter 6. Stuck-at faults can be considered as TDFs having infinite delay. Hence, the TDF Automatic Test Pattern Generation (ATPG) tests can detect both TDFs and stuck-at faults. By removing the stuck-at faults being detected by the given TDF ATPG tests, the tests that target stuck-at faults can be reduced, and the reduced stuck-at fault set results in fewer stuck-at ATPG patterns. The structural test time is reduced while keeping the same test coverage. This TDF grading is performed with the same ATPG tool used to generate the stuck-at and TDF ATPG tests. To expedite the mixed-signal design verification of complex SoC, analog behavioral modeling methods and strategies are addressed in Chapter 7 and case studies for detailed verification with actual mixed-signal design are ad- dressed in Chapter 8. Analog modeling effort can enhance verification quality for a mixed-signal design with less turnaround time, and it enables compatible integration of the mixed-signal design cores into the SoC. The modeling process may reveal any potential design errors or incorrect testbench setup, and it results in minimizing unnecessary debugging time for quality devices. Two mixed-signal design cases were verified by me using the analog models. A fully hierarchical digital-to-analog converter (DAC) model is implemented and silicon mismatches caused by process variation are modeled and inserted into the DAC model, and the calibration algorithm for the DAC is successfully verified by model-based simulation at the full DAC-level. When the mismatch amount is increased and exceeded the calibration capability of the DAC, the simulation results show the increased calibration error with some outliers. This verification method can identify the saturation range of the DAC and predict the yield of the devices from process variation. A phase-locked loop (PLL) design cases were also verified by me using the analog model. Both open-loop PLL model and closed-loop PLL model cases are presented. Quick bring-up of open-loop PLL model provides low simulation overhead for widely-used PLLs in the SOC and enables early starting of design verification for the upper-level design using the PLL generated clocks. Accurate closed-loop PLL model is implemented for DCO-based PLL design, and the mixed-simulation with analog models and schematic designs enables flexible analog verification. Only focused analog design block is set to the schematic design and the rest of the analog design is replaced by the analog model. Then, this scaled-down SPICE simulation is performed about 10 times to 100 times faster than full-scale SPICE simulation. The analog model of the focused block is compared with the scaled-down SPICE simulation result and the quality of the model is iteratively enhanced. Hence, the analog model enables both compatible integration and flexible analog design verification. This dissertation contributes to reduce test time and to enhance test quality, and helps to set up efficient production testing flows. Depending on the size and performance of CUT, proper testing schemes can maximize the efficiency of production testing. The topics covered in this dissertation can be used in optimizing the test flow and selecting the final production tests to achieve maximum test capability. In addition, the strategies and benefits of analog behavioral modeling techniques that I implemented are presented, and actual verification cases shows the effectiveness of analog modeling for better quality SoC products.Electrical and Computer Engineerin

Using UAV-Based Imagery to Determine Volume, Groundcover, and Growth Rate Characteristics of Lentil (Lens culinaris Medik.)

Plant growth rate is an essential phenotypic parameter for crop physiologists and plant breeders to understand in order to quantify potential crop productivity based on specific stages throughout the growing season. While plant growth rate information can be attained though manual collection of biomass, this procedure is rarely performed due to the prohibitively large effort and destruction of plant material that is required. Unmanned Aerial Vehicles (UAVs) offer great potential for rapid collection of imagery which can be utilized for quantification of plant growth rate. In this study, six diverse lines of lentil were grown in three replicates of microplots with six biomass collection time-points throughout the growing season over five site-years. Aerial imagery of each biomass collection time point was collected from a UAV and utilized to produce stitched two-dimensional orthomosaics and three-dimensional point clouds. Analysis of this imagery produced quantification of groundcover and vegetation volume on an individual plot basis. Comparison with manually-measured above-ground biomass suggests strong correlation, indicating great potential for UAVs to be utilized in plant breeding programs for evaluation of groundcover and vegetation volume. Nonlinear logistic models were fit to multiple data collection points throughout the growing season. The growth rate and G50, which is the number of growing degree days (GDD) required to accumulate 50 % of maximum growth, parameters of the model are capable of quantifying growth rate, and have potential utility in plant research and plant breeding programs. Predicted maximum volume was identified as a potential proxy for whole-plot biomass measurement. Six new phenotypes have been described that can be accurately and efficiently collected from field trials with the use of UAV’s or other overhead image-collection systems. These phenotypes are; Area Growth Rate, Area G50, Area Maximum Predicted Growth, Volume Growth Rate, Volume G50, and Volume Maximum Predicted Growth

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

A MULTISCALE INVESTIGATION INTO THE EFFECTS OF AGRICULTURE ON FLOOD HYDROLOGY IN SOUTHWEST ENGLAND

In the UK, perceived increases ih high impact flood events over the last decade and broad scale recognition of the enhanced flood risks associated with future climate change predictions, have reinforced the need for improved understanding and management of processes governing peak flow responses. This thesis investigates the effects of agricultural land uses on the hydrology of rural areas at a range of spatial and temporal scales. At the catchment scale, 48 catchments and subcatchments distributed across the south western counties of Cornwall, Devon, Somerset and Dorset were investigated. A suite of multivariate statistical techniques, including Direct (Redundancy Analysis) and Indirect (Principal Components Analysis) Ordination were used to explore catchment responses to four major storm events, selected from the wet autumn/winter of 2000-2001. A Geographic Information System. (GIS) incorporating the Hydrology of Soil Types (HOST) soil classification system and Land Cover Map 2000 satellite imagery data was developed to parameterise catchment physiographic variables and calculate the extent of 27 land use classes. Analysis of regional trends in erivironmental variables and two multivariate runoff datasets (R1 and R2) identified land use as the principal control of streamflow responses to extreme storm events. Land use, soil and geology parameters together explained 84% (R1) and 78% (R2) of the Variance in runoff for the same four storms. Grassland and improved grassland were consistent characteristics of catchments generating higher runoff volumes per unit area. Similarities in the hydrological behaviours of the Camel catchment and the De Lank subcatchment supported a dominant control on peak flows by runoff from grazed upland areas. A longer-term study of the River Camel catchment (1965-2000) revealed a 20% increase in the magnitude of the one in 25 year flow. Daily rainfall totals aggregated at monthly, seasonal and annual timescales and agricultural census data for the years 1969, 1979, 1988, 1997 and 2000 were examined to determine the influence of climate and land use changes on the enhanced streamflow response. Increases in the frequency and magnitude of peak flows were attributed to the cumulative impacts of a subtle, long-term rise in October rainfall totals, coupled with local urban development, the expansion of arable cultivation on highly connected slopes in the lower catchment and a rise in the intensity of grazing in the upper catchment At the field scale, characterisation of the textural, structural and ^hydraulic properties of soils subject to different land managements, including continuous cereal cultivation (CC), semi permanent pasture (SPP), permanent pasture (PP) and farm woodland (FW), identified a link between land use 'and the structural stability of the surface horizon. Marked differences in the percentage of water stable aggregates (WSA>2.8mm) between the topsoils of FW (66%) and.PP (71%), SPP (11%) and CC (6%) helped to explain differences in saturated hydraulic conductivity that were in the order FW>PP>SPP>CC, Laboratory rainfall simulations revealed slower wetting rates and higher average soil moisture percentages at near-saturation in FW and PP soil plots compared to SPP and CC soil plots that resulted from higher total porosities under FW and PP. Agricultural management systems are therefore capable of playing an important role in attenuating peak flow responses to storm events through considered land management which ameliorates or prevents soil structural deterioration and encourages the movement of water into storages within the hillslope. The adoption of specific measures, such as the introduction of buffer strips, widening of hedgerows or the introduction of forested areas to act as sinks, may serve to disconnect hydrofogical pathways from the main channel by providing a barrier to runoff, thereby reducing the upslope contributing area

Design and Validation of Network-on-Chip Architectures for the Next Generation of Multi-synchronous, Reliable, and Reconfigurable Embedded Systems

NETWORK-ON-CHIP (NoC) design is today at a crossroad. On one hand, the design principles to efficiently implement interconnection networks in the resource-constrained on-chip setting have stabilized. On the other hand, the requirements on embedded system design are far from stabilizing. Embedded systems are composed by assembling together heterogeneous components featuring differentiated operating speeds and ad-hoc counter measures must be adopted to bridge frequency domains. Moreover, an unmistakable trend toward enhanced reconfigurability is clearly underway due to the increasing complexity of applications. At the same time, the technology effect is manyfold since it provides unprecedented levels of system integration but it also brings new severe constraints to the forefront: power budget restrictions, overheating concerns, circuit delay and power variability, permanent fault, increased probability of transient faults. Supporting different degrees of reconfigurability and flexibility in the parallel hardware platform cannot be however achieved with the incremental evolution of current design techniques, but requires a disruptive approach and a major increase in complexity. In addition, new reliability challenges cannot be solved by using traditional fault tolerance techniques alone but the reliability approach must be also part of the overall reconfiguration methodology. In this thesis we take on the challenge of engineering a NoC architectures for the next generation systems and we provide design methods able to overcome the conventional way of implementing multi-synchronous, reliable and reconfigurable NoC. Our analysis is not only limited to research novel approaches to the specific challenges of the NoC architecture but we also co-design the solutions in a single integrated framework. Interdependencies between different NoC features are detected ahead of time and we finally avoid the engineering of highly optimized solutions to specific problems that however coexist inefficiently together in the final NoC architecture. To conclude, a silicon implementation by means of a testchip tape-out and a prototype on a FPGA board validate the feasibility and effectivenes

Towards an embedded board-level tester: study of a configurable test processor

The demand for electronic systems with more features, higher performance, and less power consumption increases continuously. This is a real challenge for design and test engineers because they have to deal with electronic systems with ever-increasing complexity maintaining production and test costs low and meeting critical time to market deadlines. For a test engineer working at the board-level, this means that manufacturing defects must be detected as soon as possible and at a low cost. However, the use of classical test techniques for testing modern printed circuit boards is not sufficient, and in the worst case these techniques cannot be used at all. This is mainly due to modern packaging technologies, a high device density, and high operation frequencies of modern printed circuit boards. This leads to very long test times, low fault coverage, and high test costs. This dissertation addresses these issues and proposes an FPGA-based test approach for printed circuit boards. The concept is based on a configurable test processor that is temporarily implemented in the on-board FPGA and provides the corresponding mechanisms to communicate to external test equipment and co-processors implemented in the FPGA. This embedded test approach provides the flexibility to implement test functions either in the external test equipment or in the FPGA. In this manner, tests are executed at-speed increasing the fault coverage, test times are reduced, and the test system can be adapted automatically to the properties of the FPGA and devices located on the board. An essential part of the FPGA-based test approach deals with the development of a test processor. In this dissertation the required properties of the processor are discussed, and it is shown that the adaptation to the specific test scenario plays a very important role for the optimization. For this purpose, the test processor is equipped with configuration parameters at the instruction set architecture and microarchitecture level. Additionally, an automatic generation process for the test system and for the computation of some of the processor’s configuration parameters is proposed. The automatic generation process uses as input a model known as the device under test model (DUT-M). In order to evaluate the entire FPGA-based test approach and the viability of a processor for testing printed circuit boards, the developed test system is used to test interconnections to two different devices: a static random memory (SRAM) and a liquid crystal display (LCD). Experiments were conducted in order to determine the resource utilization of the processor and FPGA-based test system and to measure test time when different test functions are implemented in the external test equipment or the FPGA. It has been shown that the introduced approach is suitable to test printed circuit boards and that the test processor represents a realistic alternative for testing at board-level.Der Bedarf an elektronischen Systemen mit zusätzlichen Merkmalen, höherer Leistung und geringerem Energieverbrauch nimmt ständig zu. Dies stellt eine erhebliche Herausforderung für Entwicklungs- und Testingenieure dar, weil sie sich mit elektronischen Systemen mit einer steigenden Komplexität zu befassen haben. Außerdem müssen die Herstellungs- und Testkosten gering bleiben und die Produkteinführungsfristen so kurz wie möglich gehalten werden. Daraus folgt, dass ein Testingenieur, der auf Leiterplatten-Ebene arbeitet, die Herstellungsfehler so früh wie möglich entdecken und dabei möglichst niedrige Kosten verursachen soll. Allerdings sind die klassischen Testmethoden nicht in der Lage, die Anforderungen von modernen Leiterplatten zu erfüllen und im schlimmsten Fall können diese Testmethoden überhaupt nicht verwendet werden. Dies liegt vor allem an modernen Gehäuse-Technologien, der hohen Bauteildichte und den hohen Arbeitsfrequenzen von modernen Leiterplatten. Das führt zu sehr langen Testzeiten, geringer Testabdeckung und hohen Testkosten. Die Dissertation greift diese Problematik auf und liefert einen FPGA-basierten Testansatz für Leiterplatten. Das Konzept beruht auf einem konfigurierbaren Testprozessor, welcher im On-Board-FPGA temporär implementiert wird und die entsprechenden Mechanismen für die Kommunikation mit der externen Testeinrichtung und Co-Prozessoren im FPGA bereitstellt. Dadurch ist es möglich Testfunktionen flexibel entweder auf der externen Testeinrichtung oder auf dem FPGA zu implementieren. Auf diese Weise werden Tests at-speed ausgeführt, um die Testabdeckung zu erhöhen. Außerdem wird die Testzeit verkürzt und das Testsystem automatisch an die Eigenschaften des FPGAs und anderer Bauteile auf der Leiterplatte angepasst. Ein wesentlicher Teil des FPGA-basierten Testansatzes umfasst die Entwicklung eines Testprozessors. In dieser Dissertation wird über die benötigten Eigenschaften des Prozessors diskutiert und es wird gezeigt, dass die Anpassung des Prozessors an den spezifischen Testfall von großer Bedeutung für die Optimierung ist. Zu diesem Zweck wird der Prozessor mit Konfigurationsparametern auf der Befehlssatzarchitektur-Ebene und Mikroarchitektur-Ebene ausgerüstet. Außerdem wird ein automatischer Generierungsprozess für die Realisierung des Testsystems und für die Berechnung einer Untergruppe von Konfigurationsparametern des Prozessors vorgestellt. Der automatische Generierungsprozess benutzt als Eingangsinformation ein Modell des Prüflings (device under test model, DUT-M). Das entwickelte Testsystem wurde zum Testen von Leiterplatten für Verbindungen zwischen dem FPGA und zwei Bauteilen verwendet, um den FPGA-basierten Testansatz und die Durchführbarkeit des Testprozessors für das Testen auf Leiterplatte-Ebene zu evaluieren. Die zwei Bauteile sind ein Speicher mit direktem Zugriff (static random-access memory, SRAM) und eine Flüssigkristallanzeige (liquid crystal display, LCD). Die Experimente wurden durchgeführt, um den Ressourcenverbrauch des Prozessors und Testsystems festzustellen und um die Testzeit zu messen. Dies geschah durch die Implementierung von unterschiedlichen Testfunktionen auf der externen Testeinrichtung und dem FPGA. Dadurch konnte gezeigt werden, dass der FPGA-basierte Ansatz für das Testen von Leiterplatten geeignet ist und dass der Testprozessor eine realistische Alternative für das Testen auf Leiterplatten-Ebene ist

Satellite Networks: Architectures, Applications, and Technologies

Since global satellite networks are moving to the forefront in enhancing the national and global information infrastructures due to communication satellites' unique networking characteristics, a workshop was organized to assess the progress made to date and chart the future. This workshop provided the forum to assess the current state-of-the-art, identify key issues, and highlight the emerging trends in the next-generation architectures, data protocol development, communication interoperability, and applications. Presentations on overview, state-of-the-art in research, development, deployment and applications and future trends on satellite networks are assembled

Deep water uptake of perennial crops. A case study on intermediate wheatgrass and alfalfa.

The perfect storm. That is the term used by Gerald C. Nelson to describe the triple challenge of increasing food production while adapting to climate change and reducing the environmental impact of agricultural systems. Nowadays, conventional farming systems are showing some limitations, such as low resources use efficiency and poor ecosystems services that appear to be associated to the loss of plant diversity and perenniality in crop rotations. In addition, water, the most important yield limiting factor worldwide, will increasingly restrict food production in the future due to rainfall shortage and increase in human consumption. In such context, perennial crops, with denser and deeper root system could use resources in deep soil layers that are logically inaccessible to crops with shallower root system. The goal of this thesis was therefore to investigate the root growth and water uptake capacity of intermediate wheatgrass (Kernza®) and alfalfa, two deep rooted perennial crops, under field conditions and at great soil depth (i.e. 1.0-2.5 m). Maintaining hydraulic continuity along the soil-plant-atmosphere continuum is a prerequisite for deep water uptake. At the plant level, hydraulic conductivity depends on complex anatomical and physiological processes among which the root system constitutes the second largest resistance to water flow. Therefore, in depth characterisation of root and xylem anatomy was done to understand the hydraulic properties of the crop root systems, with a focus on their evolution with soil depth. Crops were grown in the field, rhizoboxes, mesocosms and solution culture to take into account the variability of root type and soil depth as well as growing environment. For both crops, axial hydraulic conductance decreased with soil depth and along individual root segment. Alfalfa roots had greater axial hydraulic conductance in comparison to intermediate wheatgrass roots, especially at depth. Root and xylem anatomy were highly variable across crop species, root types and growing environments. In parallel, a combination of imaging and sensor technology, stable isotope techniques and a modelling approach was used to study root growth and water uptake under field conditions during the 2018-2019 seasons. Both crops presented roots down to 2.0 m soil depth that were active in terms of water uptake. Alfalfa had greater root length at depth and absorbed twice as much water below 1 m soil depth, than intermediate wheatgrass. For both crops, model simulations predicted that water uptake in deep soil layers (i.e. 1.5 – 2.0 m) increase (i.e.>30%) under dry conditions. This thesis brings insights into the understudied field of root growth and water uptake at great soil depth. Particular efforts were put in understanding the environmental and agricultural contexts in which deep root growth, deep water uptake and the development of perennial cropping systems would be possible and favourable