A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Investigation of External Factors for Wireless Capacitive Power Transfer Systems

Capacitive power transfer (CPT) technology has gained more and more importance in recent years. This paper investigates the effects of temperature and relative humidity on CPT system performance. The conventional four-plate horizontal and vertical coupler structures are built to observe the variations of coupling capacitances under external factors. The pressure of the coupler ambient is kept constant, and the effects of temperature and relative humidity are reviewed separately. The different temperature (25 - 105 °C) and relative humidity (43 - 80% RH) levels are reviewed in these scenarios. The obtained results indicate that the values of coupling capacitances are inversely proportional to the temperature level, whereas the values of coupling capacitances are directly proportional to the relative humidity level. In addition, the visible changes happen in coupling capacitances after 45 °C and 55 °C for horizontally and vertically arranged four-plate coupler structures, respectively. It is also observed that relative humidity level becomes a critical point after 60% RH for both coupler structures. Among the coupling capacitances, the main capacitances are the most affected during the variations for both couplers. This study is expected to be a reference for the researchers on external factors in CPT systems

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

GaN-on-Si 기반의 고주파/고전력 소자의 제작 및 특성 분석

학위논문 (박사)-- 서울대학교 대학원 : 전기·정보공학부, 2016. 2. 서광석.Owing to the unique capabilities of achieving high current density, high breakdown voltage, high cut-off frequency and high operating temperature, AlGaN/GaN high electron mobility transistors (HEMTs) are emerging as promising candidates for RF power amplifier and power switching devices. Nevertheless, despite the great potential of these new technologies, they still suffer from physical and fabrication issues which may prevent devices fabricated on GaN from achieving the performance required. This thesis presents a comprehensive study on the development of GaN-based high frequency, high power transistors. This work can be divided into two parts, namely D-mode AlGaN/GaN schottky HEMTs on silicon substrate for high power X-band operation and E-mode Si3N4/AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistors (MIS-HFETs) for power switching devices. One of the main obstacle is the trapping effects, may be exacerbated when devices are operated in Radar systems. In this work, we will use a novel fluoride-based plasma treatment technique to reduce trapping phenomenon which originated from the surface, and then apply this treatment technique in conjunction with a field plate structure to a device for GaN-based RF applications. To improve overall device performance, a backend process with individually grounded source via formation has been developed to integrate large periphery devices. Based upon it, GaN HEMT amplifier with single chip of 3.6 mm gate periphery has been successfully developed. It exhibits very high power density of 8.1 W/mm with 29.4 W output power under VDS = 38 V pulse operating condition. Compared to the conventional depletion-mode AlGaN/GaN (D-mode), Enhancement mode (E-mode) devices are attracting a great interest as they allow simplistic circuity and safe operation. It is difficult to obtain E-mode operation with a low on-resistance and a high breakdown voltage. A gate recess technique will be crucial to realize an enhancement-mode operation and improve the transfer characteristics. To reduce the on resistance and enhance the drain current density, partially recessed MIS-HFETs are investigated. The gate recess was carried out using a low-damage Cl2/BCl3-based RIE where the target etch depth was remains AlGaN barrier layer in order to improve the transfer characteristics. The occurring degradation of the mobility due to plasma etching-induced damage and scattering effect were effectively removed by partial gate recess technique. The technologies we developed have helped to give definitive direction in developing GaN-based high frequency, high power transistors.CHAPTER 1 Introduction 1 1.1 Background 1 1.2 Substrate for Epitaxial Growth of GaN 6 1.3 Research Aims and Objectives 8 1.4 Organization of Thesis 9 1.5 References 11 CHAPTER 2 Technology Development and Fabrication of AlGaN/GaN HEMTs on Si substrate 15 2.1 Introduction 15 2.2 Epitaxy Layer Structure 16 2.3 Device Fabrication Processes 17 2.3.1 Sample Preparation 18 2.3.2 Mesa Isolation 19 2.3.3 Ohmic Formation 20 2.3.4 Schottky Contacts 24 2.3.5 Contac Pads 26 2.3.6 Air-bridge Interconnection 26 2.4 References 33 CHAPTER 3 Au-Plated Through-Wafer Vias for AlGaN/GaN HEMTs on Si substrate 36 3.1 Introduction 36 3.2 Via-hole Fabrication 37 3.2.1 Experiments 38 3.2.2 Tapered Source Via Formation 40 3.2.3 GaN Etching Process 50 3.2.4 Au Electroplating 53 3.3 Back-side Process Flows 54 3.3.1 Individual Source Via 58 3.3.2 Au-Sn Eutectic Solder Die Attach 60 3.3.3 Thermal Resistance Measurement 61 3.4 References 66 CHAPTER 4 AlGaN/GaN HEMTs for RF applications 69 4.1 Introduction 69 4.2 Advantages of AlGaN/GaN HEMTs for RF Power Devices 70 4.3 RF Performance Limitations 73 4.3.1 Surface States 73 4.3.2 Current Collapse Phenomenon 75 4.4 Device Fabrication 79 4.4.1 Device Layout 85 4.4.2 Slant Gate Process 86 4.4.3 Fluorine Plasma Treatment process 89 4.5 Device Characterization 93 4.5.1 DC and Small Signal Performance 93 4.5.2 Pulse Characteristics 98 4.5.3 Large Signal Performance 99 4.6 Wide Periphery Devices 103 4.6.1 Large Signal Performance 104 4.7 Summary 109 4.8 Reference 110 CHAPTER 5 AlGaN/GaN HEMTs for Power applications 115 5.1 Introduction 115 5.2 Advantages of AlGaN/GaN HEMTs for Power Switching Devices 116 5.2.1 Enhancement-mode Operation 117 5.2.2 High Breakdown Voltage 119 5.3 Device Fabrication 121 5.3.1 Gate Recess Process 124 5.3.2 Plasma Enhance ALD SiNx Film 138 5.4 Characterization for Normally-off GaN Transistors 140 5.4.1 DC Characteristics 140 5.4.2 Breakdown Voltage Characteristics 144 5.4.3 Dynamic Ron Characteristics 146 5.5 Summary 148 5.6 Reference 149 CHAPTER 6 Conclusions and Future Works 155 6.1 Conclusions and Future Works 155 Appendix 159 Abstract in Korean 169 Research Achievements 174Docto

Analyse et caractérisation des couplages substrat et de la connectique dans les circuits 3D : Vers des modèles compacts

The 3D integration is the most promising technological solution to track the level of integration dictated by Moore's Law (see more than Moore, Moore versus more). It leads to important research for a dozen years. It can superimpose different circuits and components in one box. Its main advantage is to allow a combination of heterogeneous and highly specialized technologies for the establishment of a complete system, while maintaining a high level of performance with very short connections between the different circuits. The objective of this work is to provide consistent modeling via crossing, and / or contacts in the substrate, with various degrees of finesse / precision to allow the high-level designer to manage and especially to optimize the partitioning between the different strata. This modelization involves the development of multiple views at different levels of abstraction: the physical model to "high level" model. This would allow to address various issues faced in the design process: - The physical model using an electromagnetic simulation based on 2D or 3D ( finite element solver ) is used to optimize the via (materials, dimensions etc..) It determines the electrical performance of the via, including high frequency. Electromagnetic simulations also quantify the coupling between adjacent via. - The analytical compact of via their coupling model, based on a description of transmission line or Green cores is used for the simulations at the block level and Spice type simulations. Analytical models are often validated against measurements and / or physical models.L’intégration 3D est la solution technologique la plus prometteuse pour suivre le niveau d’intégration dictée par la loi de Moore (cf. more than Moore, versus more Moore). Elle entraine des travaux de recherche importants depuis une douzaine d’années. Elle permet de superposer différents circuits et composants dans un seul boitier. Son principal avantage est de permettre une association de technologies hétérogènes et très spécialisées pour la constitution d’un système complet, tout en préservant un très haut niveau de performance grâce à des connexions très courtes entre ces différents circuits. L’objectif de ce travail est de fournir des modélisations cohérentes de via traversant, ou/et de contacts dans le substrat, avec plusieurs degrés de finesse/précision, pour permettre au concepteur de haut niveau de gérer et surtout d’optimiser le partitionnement entre les différentes strates. Cette modélisation passe par le développement de plusieurs vues à différents niveaux d’abstraction: du modèle physique au modèle « haut niveau ». Elle devait permettre de répondre à différentes questions rencontrées dans le processus de conception :- le modèle physique de via basé sur une simulation électromagnétique 2D ou 3D (solveur « éléments finis ») est utilisé pour optimiser l’architecture du via (matériaux, dimensions etc.) Il permet de déterminer les performances électriques des via, notamment en haute fréquence. Les simulations électromagnétiques permettent également de quantifier le couplage entre via adjacents. - le modèle compact analytique de via et de leur couplage, basé sur une description de type ligne de transmission ou noyaux de Green, est utilisé pour les simulations au niveau bloc, ainsi que des simulations de type Spice. Les modèles analytiques sont souvent validés par rapport à des mesures et/ou des modèles physiques

Transfer printing based microassembly and colloidal quantum dot film integration

Micro / nanoscale manufacturing requires unique approaches to accommodate the immensely different characteristics of the miniscule objects due to their high surface area to volume ratio when compared with macroscale objects. Therefore, surface forces are much more dominating than body forces, which causes the significant difficulty of miniscule object manipulation. Because of this challenge, monolithic microfabrication relying on photolithography has been the primary method to manufacture micro / nanoscale structures and devices in place of microassembly. However, by virtue of the two-dimensional (2D) nature of photolithography, formation of complex 3D shape architectures via monolithic microfabrication is inherently limited, which would otherwise enable improvements in performance and novel functionalities of devices. Furthermore, monolithic microfabrication is compatible only with materials which survive in a wet condition during photolithography. Delicate nanomaterials such as colloidal quantum dots cannot be processed via monolithic microfabrication. In this context, transfer printing has emerged as a method to transfer heterogeneous material pieces from their mother substrates to a foreign substrate utilizing a polymeric stamp in a dry condition. In this thesis, advanced modes of transfer printing are studied and optimized to enable a 3D microassembly called ‘micro-Lego’ and a novel strategy of quantum dot film integration. Micro-Lego involves transfer printing for material piece pick-and-place and thermal joining for irreversible permanent bonding of placed material pieces. A microtip elastomeric stamp is designed to advance transfer printing and thermal joining processes are optimized to ensure subsequent material bonding. The mechanical joining strength between material pieces assembled by micro-Lego are characterized by means of blister tests and the nanoindentation. Moreover, the electrical contact between two conducting materials formed by micro-Lego are examined. Lastly, inspired from the subtractive transfer printing technique, protocols of quantum dot film patterning using polymeric stamps made of a shape memory polymer as well as a photoresist are established for the convenient integration of quantum dots in various geometries and configurations as desired. Transfer printing-based micro / nanoscale manufacturing presented in this thesis opens up new pathways to manufacture not only complex 3D functional micro devices but also high resolution nano devices for unparalleled performance or for an unusual functionality, which are unattainable through monolithic microfabrication

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.Comment: 53 Page

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Heterogeneous Integrated Photonic Transceiver on Silicon

The demand for high-speed and low-cost short-distance data links, eventually for chip-level optical communication, has led to large efforts to develop high density photonics integrated circuits (PICs) to decrease the power consumption and unit price. Particularly, silicon based photonic integration promise future high-speed and cost-effective optical interconnects to enable exascale performance computers and datacenters. High-level integration of all photonics components on chip, including high speed modulators and photodetectors, and especially lasers, is required for scalable and energy efficient system topology designs. This is enabled by silicon-based heterogeneous integration approach, which transfers different material systems to the silicon substrate with a complementary metal–oxide–semiconductor (CMOS) compatible process. In this thesis, our work focuses on the development of silicon photonic integrated circuit in the applications of high speed chip level optical interconnects. A full library of functional devices is demonstrated on silicon, including low threshold distributed feedback (DFB) lasers as a low power laser source; high extinction ratio and high speed electroabsorption modulators (EAM) and ultra-linear Mach-Zehnder interferometer (MZI) modulators for signal modulation in the data transmitter; high speed photodetectors for the data receiver; and low loss silicon components, such as arrayed waveguide grating (AWG) routers and broadband MZI based switches. The design and characterization of those devices are discussed in this thesis. A highly integrated photonic circuit can be achieved with co-design and co-process of all types of functional photonic devices. Selective die bonding method is performed to integrate multiple III-V dies with different band-gap onto a single photonic die. A reconfigurable network-on-chip circuit was proposed and demonstrated, with state-of-the-art high-speed silicon transceiver chip. With over 400 active and passive components heterogeneously integrated on silicon, photonic circuit with multiple- wavelength-division multiplexing (WDM) transceiver nodes achieved a total capacity up to 8×8×40 Gbps. This high capacity and dense integrated heterogenous circuit shows its potential as a solution for future ultra-high speed inter- and intra-chip interconnects

Infrared Photodetectors based on InSb and InAs Nanostructures via Heterogeneous Integration-Rapid Melt Growth and Template Assisted Selective Epitaxy

Monolithic heterogeneous integration of III-V semiconductors with the contemporary Si Complementary Metal Oxide Semiconductor (CMOS) technology has instigated a wide range of possibilities and functionalities in the semiconductor industry, in the field of digitalcircuits, optical sensors, light emitters, and high-frequency communication devices. However, the integration of III-V semiconductorsis not trivial due to the differences in lattice parameters, polarity, and thermal expansion coefficient. This thesis explores two integrationtechniques to form III-V nanostructures with potential applications in the infrared detection field.The first technique implemented in this thesis work is the Rapid Melt Growth technique. InSb, which has a large lattice mismatch(19%) to Si, is used to demonstrate the RMG integration technique. A flash lamp with a millisecond annealing technique is utilized tomelt and recrystallize amorphous InSb material to form a single crystalline material. The development of the fabrication process andthe experimental results for obtaining a single crystalline InSb-on-insulator from a Si seed area through the RMG process are presented.Electron Back Scatter Diffraction (EBSD) technique was employed to understand the crystal quality, orientation, and defects in theRMG InSb nanostructures. The InSb nanostructures have a resistivity of 10 mΩ cm, similar to the VLS-grown InSb nanowires.Mobility ranging from 3490 - 877 cm2/ V sec was extracted through Hall and Van der Pauw measurements. Finally, we report the firstmonolithic integrated InSb nanostructure photodetector on Si through the RMG process. Detailed optical and electrical characterizationof the device, including the spectrally resolved photocurrent and the temperature-dependent dark current, is studied. The thesis presentsan InSb photodetector with a stable photodetector with a responsivity of 0.5 A/W at 16 nW illumination and millisecond time response.The second integration technique implemented in this thesis work is Template Assisted Selective Epitaxy. Here, the versatility ofTASE technique to integrate InAs nanowires on W metal seed is demonstrated. This technique enables the feasibility of integratingIII-V semiconductors to back -end of the line integration with Si CMOS technology. EBSD technique was utilized to study andobtain the statistics on the single crystalline InAs nanowires grown from different diameter templates. We also demonstrate thepossibility of achieving an nBn InAs detector using TASE on W approach. This technique is a promising step towards developinghigh operating temperature (HOT) monolithic integrated mid-infrared detectors. Thus, the results of this thesis provide theperspective into two viable CMOS-compatible III-V integration techniques that could be utilized for photodetector applications at areduced cost