핀펫 소자에서의 핫캐리어 신뢰성 분석

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 신형철.CMOS 로직 소자는 퍼포먼스를 향상시키기 위해 지속적으로 축소화 되고 있다. 하지만 구조 파라미터들의 축소화에 비해 동작 전압은 충분히 감소하지 않는다. 따라서 소자 내 수직 전계나 온도가 증가하는 추세이기 때문에 신뢰성은 계속해서 문제가 되고 있다. 최근 3D 소자의 신뢰성에 대한 연구는 많이 진행되고 있지만 empirical 모델링과 관련된 연구가 대부분이다. 따라서 본 연구에서는 실제 측정을 기반으로 시뮬레이션을 이용하여 물리적 이론 중심으로 로직 소자의 핫캐리어 신뢰성을 분석하였다. 먼저 핫캐리어 모델의 정확성을 향상시키기 위해서 TCAD 시뮬레이션에 electron-electron scattering을 적용하였다. 추가적으로 3D FinFET의 측정 데이터와 calibration을 진행하여 모델의 정합성을 확인하였다. calibration 과정에서는 모든 scattering 메커니즘을 고려하기 위해 다양한 전압과 온도 조건이 필요하다. 따라서 다양한 전압 조건에 따른 HCD를 분석하고, calibration을 진행하여 HCD 모델의 파라미터를 추출하였다. 다음으로 전압 조건에 따른 HCD의 온도 경향성을 분석하였다. oxide trap과 달리 interface trap은 전압 조건에 따라 다른 온도 경향성을 보인다. 따라서 interface trap을 3가지 성분으로 분리하여 각 성분의 온도 경향성을 분석하였다. Multiple particle process(MP)과 field enhanced thermal degradation process(FP)는 전압 조건과 상관없이 일정한 온도 경향성을 가진다. 반면 Single particle process(SP)는 scattering의 영향을 받기 때문에 온도 경향성은 전압 조건에 따라 달라진다. 온도 경향성 분석 과정에서도 calibration을 진행하며 여러 번의 iteration을 통해 다양한 전압 및 온도가 고려된 파라미터를 추출한다. 추출된 파라미터를 적용한 시뮬레이션 모델은 기존의 모델보다 더 정확하게 HCD 측정 결과를 예측하였다. 결과적으로 물리적 이론에 근거하여 시뮬레이션 모델 구축함으로써 HCD 분석의 정확성을 향상시켰다. 하지만 가속 조건과 동작 조건의 self-heating 효과가 다르기 때문에 소자가 실제 CMOS 회로의 동작 조건에서 interface trap을 발생시키는 메커니즘은 다를 수 있다. 따라서 우리는 동작 영역에서의 각 성분의 비율까지 예측하였다. 마지막으로 우리는 10 nm node 소자에서 nFinFET에 비해 pFinFET에서 높은 열화가 발생하는 원인에 대해 분석하였다. pFinFET은 소스/드레인 물질로 SiGe를 사용하기 때문에 nFinFET에 비해 self-heating 효과가 심하여 소자 온도가 도 높다. 이론적으로 MP 메커니즘의 lifetime은 온도가 증가할수록 감소하기 때문에 MP에 의한 열화 또한 감소한다. 따라서 소자 온도가 더 높은 pFinFET에서 nFinFET에 비해 더 많은 MP가 발생하기 어렵다. 하지만 nFinFET 과 달리 pFinFET에서는 Si-H bond의 electron과 hole이 반응하여 interface trap을 생성시키는 RD 가 발생할 수 있다. 또한 RD는 온도가 높을수록 더 많은 열화가 발생하기 때문에, pFinFET에서 nFinFET보다 더 많은 열화가 발생하는 현상을 설명할 수 있다. 따라서 우리는 HCD 조건이지만 소자 온도가 높은 pFinFET에서 추가적인 RD 메커니즘이 발생할 수 있다고 제안한다. 다양한 전압 조건에서의 전류 열화율을 통해 주요 열화 메커니즘을 분석하였으며 pFinFET에서는 RD가 주요함을 확인하였다. 또한 TCAD 시뮬레이션을 이용하여 HCD 조건에서 발생할 수 있는 RD를 예측하였다. 그 결과 RD를 제외한 순수 hot carrier 성분은 pFinFET보다 nFinFET에서 더 많이 발생한다.CMOS logic devices have been scaled down to improve performance. However, the operating voltage is not sufficiently reduced compared to the scale down in physical dimensions. Therefore, since the electric field and temperature of the device gradually increase, reliability is still a critical issue in logic devices. Recently, many studies on the reliability of 3D devices are being conducted, but most of the studies are related to empirical modeling. Therefore, in this study, based on the actual measurement results, the hot carrier degradation(HCD) reliability of the logic device was analyzed focusing on the physical theory using Technology computer-aided design (TCAD) simulation. First, electron-electron scattering(EES) was applied to the TCAD simulation to improve the accuracy of the hot carrier model. Additionally, calibration between the measurement data of 14 nm node FinFET and the model was performed to confirm the consistency. The calibration process required various voltage and temperature conditions to account for all scattering mechanisms. Therefore, HCD was analyzed according to various voltage conditions, and the parameters of the HCD model were extracted by calibration process. Next, temperature dependence under various HCD conditions was analyzed. Unlike oxide traps, interface traps show different temperature dependence depending on HCD voltage conditions. Therefore, the interface traps were separated into three components and the temperature dependence was analyzed for each component. Multiple particle process (MP) and Field enhanced thermal degradation process (FP) have a constant temperature dependence regardless of voltage conditions. On the other hand, the temperature dependence of Single particle process (SP) varies depending on the voltage condition because SP is affected by scattering. In the process of temperature dependence analysis, calibration is also performed and parameters considering various voltages and temperatures were extracted through several iterations. The improved model to which the extracted parameters were applied showed more precise prediction of degradation compared to that of the previous model. As a results, accuracy of the HCD analysis was improved by establishing the HCD simulation framework based on physical theories. However, since the self-heating effect of the acceleration condition and the operation condition are different, the HCD mechanism that occurs in the actual CMOS circuit may also be different. Therefore, we predicted the ratio of each component under operating condition. Finally, in 10 nm node devices, we analyzed the cause of higher HCD in pFinFETs than in nFinFETs. Self-heating effect is severe in pFinFETs because SiGe is used as the source/drain material which makes the device temperature higher than nFinFETs. Theoretically, because the lifetime of multiple particle(MP) mechanism decreases as temperature increases, degradation due to MP decreases. Therefore, it is difficult for the HCD mechanisms to occur more in pFinFETs which has higher temperature than nFinFETs. However, in pFinFETs unlike nFinFETs, reaction-diffusion (RD) mechanism can occur in which holes react with the electrons of Si-H bonds to generate interface traps. Also, since RD deteriorates more as the temperature increases, the phenomenon that more degradation occurs in pFinFET than nFinFET can be explained by the RD mechanism. Therefore, we propose an additional RD mechanism that is caused by high device temperature in pFinFETs even in HCD condition. Main components were investigated through measurements of current degradation rate in various voltage conditions, and it was found that RD is dominant in pFinFETs. Also, RD that can occur in HCD condition was predicted through TCAD simulation. As a results, degradation due to pure hot carriers without RD occurs more in nFinFETs than in pFinFETs.Abstract i Chapter 1. Introduction 1 Chapter 2. Hot Carrier Degradation Model 4 2.1. Physical theory 4 2.2. TCAD simulation 8 2.3. Calibration process 14 2.4. Summary 22 Chapter 3. Analysis on Temperature Dependence of HCD 25 3.1. Introduction 25 3.2. Temperature dependence according to acceleration conditions 26 3.3. Calibration process 30 3.4. Mechanism separation 33 3.5. HCD prediction in the nominal voltage 35 3.6. Summary 36 Chapter 4. Comparative Analysis of HCD in nMOS/pMOS FinFET 39 4.1. Introduction 39 4.2. Comparison of HCD in the long/short channel FinFET 40 4.3. Self-heating effect in n/pFinFET 44 4.4. Bias Temperature Instability(BTI) in n/pFinFET 47 4.5. Summary 59 Chapter 5. Conclusion 64 Abstract in Korean 66 List of Publications 69Docto

Impact of self-heating on the statistical variability in bulk and SOI FinFETs

In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

Study of Warm Electron Injection in Double Gate SONOS by Full Band Monte Carlo Simulation

In this paper we investigate warm electron injection in a double gate SONOS memory by means of 2D full-band Monte Carlo simulations of the Boltzmann Transport Equation (BTE). Electrons are accelerated in the channel by a drain-to-source voltage VDS smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by the accumulated kinetic energy. Particle energy distribution at the semiconductor/oxide interface is studied for different bias conditions and different positions along the channel. The gate current is calculated with a continuum-based post-processing method as a function of the particle distribution obtained from Monte Carlo. Simulation results show that the gate current increases by several orders of magnitude with increasing drain bias and warm electron injection can be an interesting option for programming when short channel effects prohibit the application of larger drain bias

Transient Analysis of Warm Electron Injection Programming of Double Gate SONOS Memories by means of Full Band Monte Carlo Simulation

In this paper we investigate "Warm Electron Injection" as a mechanism for NOR programming of double-gate SONOS memories through 2D full band Monte Carlo simulations. Warm electron injection is characterized by an applied VDS smaller than 3.15 V, so that electrons cannot easily accumulate a kinetic energy larger than the height of the Si/SiO2 barrier. We perform a time-dependent simulation of the program operation where the local gate current density is computed with a continuum-based method and is adiabatically separated from the 2D full Monte Carlo simulation used for obtaining the electron distribution in the phase space. In this way we are able to compute the time evolution of the charge stored in the nitride and of the threshold voltages corresponding to forward and reverse bias. We show that warm electron injection is a viable option for NOR programming in order to reduce power supply, preserve reliability and CMOS logic level compatibility. In addition, it provides a well localized charge, offering interesting perspectives for multi-level and dual bit operation, even in devices with negligible short channel effects

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO2 was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA). MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO2/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (Rs) associated with the substrate and metal contact. The interface state density (Dit), calculated by conductance method, suggests that Dit is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit whereas crystallized HfO2 has the highest Dit. Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples. The reliability of TiN/ZrO2/Al2O3/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO2 by SPAO when SPAO is processed after high-k. GeO2 at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress. To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor