A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Statistical Methods for Semiconductor Manufacturing

In this thesis techniques for non-parametric modeling, machine learning, filtering and prediction and run-to-run control for semiconductor manufacturing are described. In particular, algorithms have been developed for two major applications area: - Virtual Metrology (VM) systems; - Predictive Maintenance (PdM) systems. Both technologies have proliferated in the past recent years in the semiconductor industries, called fabs, in order to increment productivity and decrease costs. VM systems aim of predicting quantities on the wafer, the main and basic product of the semiconductor industry, that may be physically measurable or not. These quantities are usually ’costly’ to be measured in economic or temporal terms: the prediction is based on process variables and/or logistic information on the production that, instead, are always available and that can be used for modeling without further costs. PdM systems, on the other hand, aim at predicting when a maintenance action has to be performed. This approach to maintenance management, based like VM on statistical methods and on the availability of process/logistic data, is in contrast with other classical approaches: - Run-to-Failure (R2F), where there are no interventions performed on the machine/process until a new breaking or specification violation happens in the production; - Preventive Maintenance (PvM), where the maintenances are scheduled in advance based on temporal intervals or on production iterations. Both aforementioned approaches are not optimal, because they do not assure that breakings and wasting of wafers will not happen and, in the case of PvM, they may lead to unnecessary maintenances without completely exploiting the lifetime of the machine or of the process. The main goal of this thesis is to prove through several applications and feasibility studies that the use of statistical modeling algorithms and control systems can improve the efficiency, yield and profits of a manufacturing environment like the semiconductor one, where lots of data are recorded and can be employed to build mathematical models. We present several original contributions, both in the form of applications and methods. The introduction of this thesis will be an overview on the semiconductor fabrication process: the most common practices on Advanced Process Control (APC) systems and the major issues for engineers and statisticians working in this area will be presented. Furthermore we will illustrate the methods and mathematical models used in the applications. We will then discuss in details the following applications: - A VM system for the estimation of the thickness deposited on the wafer by the Chemical Vapor Deposition (CVD) process, that exploits Fault Detection and Classification (FDC) data is presented. In this tool a new clustering algorithm based on Information Theory (IT) elements have been proposed. In addition, the Least Angle Regression (LARS) algorithm has been applied for the first time to VM problems. - A new VM module for multi-step (CVD, Etching and Litography) line is proposed, where Multi-Task Learning techniques have been employed. - A new Machine Learning algorithm based on Kernel Methods for the estimation of scalar outputs from time series inputs is illustrated. - Run-to-Run control algorithms that employ both the presence of physical measures and statistical ones (coming from a VM system) is shown; this tool is based on IT elements. - A PdM module based on filtering and prediction techniques (Kalman Filter, Monte Carlo methods) is developed for the prediction of maintenance interventions in the Epitaxy process. - A PdM system based on Elastic Nets for the maintenance predictions in Ion Implantation tool is described. Several of the aforementioned works have been developed in collaborations with major European semiconductor companies in the framework of the European project UE FP7 IMPROVE (Implementing Manufacturing science solutions to increase equiPment pROductiVity and fab pErformance); such collaborations will be specified during the thesis, underlying the practical aspects of the implementation of the proposed technologies in a real industrial environment

Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

On improvements in metal oxide based flexible transistors through systematic evaluation of material properties

Thin-film metal oxide (MOx) semiconductors have opened the way to a new generation of electronics based on their unique properties. With mobilities, mu, of up to 80 cm2V-1s-1, metal oxides do not rival crystalline silicon (mu~1000 cm2V-1s-1) for complex applications. But such oxides do have three unique characteristics driving great interest: their mobilities persist in the amorphous form, contrary to the thousandfold drop seen in silicon; they are transparent; and they can be processed at, or near, room temperature. Most work on MOx semiconductors, in particular indium gallium zinc oxide (IGZO), has focused on display applications, where MOx thin-film transistors (TFTs) are used to drive individual pixels, reducing power consumption by blocking less light than alternatives, and allowing smaller pixels due to reduced TFT sizes. Such work has seen great advances in IGZO, but has generally not considered the thermal budget during production. By utilising the low temperature processing possible with MOx, a new world of applications becomes possible: flexible electronics. This work aims to improve the characteristics of TFTs based on amorphous IGZO (a-IGZO) through detailed study of the thin-film structure in relation to functional performance, looking at the material structure of three critical layers in an a-IGZO TFT. A study of optimisation of a dielectric layer of Al2O3, deposited by atomic layer deposition (ALD), is presented. This dielectric, between the a-IGZO and the gate electrode, shows a three-layer substructure in what has previously been regarded as a single homogeneous layer. A study of the insulating Al2O3 buffer layer below the a-IGZO compared the properties of Al2O3 deposited by ALD and sputtering. Sputtered material has a more complex structure than ALD, consisting of multiple sublayers that correlate with the sputtering process. The structure of the two materials is discussed, and the impact on device performance considered. A detailed systematic study of the effects of annealing of a-IGZO shows a strong dependence of the density on both time and temperature. A two mechanism model is proposed which consists of structural relaxation of the amorphous material followed by absorption of oxygen from the environment. Finally, investigation of the influence of the buffer material on the a-IGZO, and the structure of this interface showed little difference in the growth of the a-IGZO, but did reveal some changes in the interface, while a systematic study of annealing effects on the a-IGZO-dielectric interface showed some interesting changes in this structure, both of which are likely to significantly impact the operational characteristics of TFT devices

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations