Design of Adiabatic MTJ-CMOS Hybrid Circuits

Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic-in-memory structures in conjunction with CMOS. In this paper, we introduce a novel adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits. The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower power consumtion compared to the previous MTJ/CMOS full adder

Conception sur mesure d'un FPGA durci aux radiations à base de mémoires magnétiques

The aim of the thesis was to show that MRAM memory has many advantages for use as a configuration memory for reconfigurable architectures and especially Field Programmable Gate-Arrays (FPGAs). This type of component is programmable and allows designing a digital circuit simply by programming memory cells that define its functionality. An FPGA is thus mainly composed of memory cells. That is why they largely determine its characteristics as its surface or power consumption and affect its performance as its speed. MRAM memories are composed of Magnetic Tunnel Junctions (JTMs) which store information in the form of a magnetization. A JTM is composed of three layers: two layers of ferromagnetic material separated by an insulating layer. One of the two ferromagnetic layers has a magnetization pinned in a fixed direction (reference layer) while the other one can have its magnetization switched between two directions (storage layer). Thus, the propagation of the electrons is changed depending on whether the two magnetizations are parallel or antiparallel that is to say that the electrical resistance of the junction changes according to the orientation of the magnetizations. It is low when the magnetizations are parallel and high when antiparallel. Writing a JTM consists in changing the orientation of the magnetization of the storage layer while reading consists in determining if the resistance is high or low. The advantages of the JTM make it a good candidate to be used as a universal memory although research efforts are still needed. However, it has many advantages such as non-volatility, fast and low power consumption compared to writing to Flash memory as well as resistance to radiation. With these advantages, we may already use it in some applications and in particular in the field of space. Indeed, its use in this area allows taking advantage of all of the benefits of JTM due to the fact that it is intrinsically immune to radiation and non-volatile. It therefore enables to make a radiation hardened and low power FPGA with new functionalities. The work of this thesis is held over three years. The first year was dedicated to the state of the art in order to learn the mechanisms of JTMs, the architecture of FPGAs, radiation hardening and low power consumption techniques as well as the operation of the tools used in microelectronics. After the first year, a new FPGA architecture concept was proposed. The second and third years were devoted to the realization of this innovation with the search for the best circuit structure and the realization of an elementary component of a FPGA and the design and manufacture of a demonstrator. The demonstrator has been successfully tested and proved the new concept. The new circuit architecture of FPGA has shown that the use of MRAM cells as configuration memories for FPGAs was particularly advantageous for future technologies.Le but de la thèse a été de montrer que les cellules mémoires MRAM présentent de nombreux avantages pour une utilisation en tant que mémoire de configuration pour les architectures reconfigurables et en particulier les FPGAs (Field Programmable Gate Arrays). Ce type de composant est programmable et permet de concevoir un circuit numérique simplement en programmant des cellules mémoires qui définissent sa fonctionnalité. Un FPGA est principalement constitué de cellules mémoires. C'est pourquoi elles déterminent en grande partie ses caractéristiques comme sa surface ou sa consommation et influencent ses performances comme sa rapidité. Les mémoires MRAM sont composées de Jonctions Tunnel Magnétiques (JTMs) qui stockent l'information sous la forme d'une aimantation. Une JTM est composée de trois couches : deux couches de matériaux ferromagnétiques séparées par une couche isolante. Une des deux couches ferromagnétiques a une aimantation fixée dans un certaine direction (couche de référence) tandis que l'autre peut voir son aimantation changer dans deux directions (couche de stockage). Ainsi, la propagation des électrons est changée suivant que les deux aimantations sont parallèles ou antiparallèles c'est-à-dire que la résistance électrique de la jonction change suivant l'orientation relative des aimantations. Elle est faible lorsque les aimantations sont parallèles et forte lorsqu'elles sont antiparallèles. L'écriture d'une JTM consiste donc à changer l'orientation de l'aimantation de la couche de stockage tandis que la lecture consiste à déterminer si l'on a une forte ou une faible résistance. Les atouts de la JTM font d'elle une bonne candidate pour être une mémoire dite universelle, bien que des efforts de recherche restent à accomplir. Cependant, elle a de nombreux avantages comme la non-volatilité, la rapidité et la faible consommation à l'écriture comparée à la mémoire Flash ainsi que la résistance aux radiations. Grâce à ces avantages, on peut déjà l'utiliser dans certaines applications et en particulier dans le domaine du spatial. En effet, l'utilisation dans ce domaine permet de tirer parti de tous les avantages de la JTM en raison du fait qu'elle est intrinsèquement immune aux radiations et non-volatile. Elle permet donc de réaliser un FPGA résistant aux radiations et avec une basse consommation et de nouvelles fonctionnalités. Le travail de la thèse s'est donc déroulé sur trois ans. La première année a d'abord été dédiée à l'état de l'art afin d'apprendre le fonctionnement des JTMs, l'architecture des FPGAs, les techniques de durcissement aux radiations et de basse consommation ainsi que le fonctionnement des outils utilisés en microélectronique. Au bout de la première année, un nouveau concept d'architecture de FPGA a été proposé. Les deuxième et troisième années ont été dédiées à la réalisation de cette innovation avec la recherche de la meilleure structure de circuit et la réalisation d'un circuit de base d'un FPGA ainsi que la conception puis la fabrication d'un démonstrateur. Le démonstrateur a été testé avec succès et a permis de prouver le concept. La nouvelle architecture de circuit de FPGA a permis de montrer que l'utilisation des mémoires MRAM comme mémoire de configuration de FPGA était avantageuse et en particulier pour les technologies futures

Conception sur mesure d'un FPGA durci aux radiations à base de mémoires magnétiques

Le but de la thèse a été de montrer que les cellules mémoires MRAM présentent de nombreux avantages pour une utilisation en tant que mémoire de configuration pour les architectures reconfigurables et en particulier les FPGAs (Field Programmable Gate Arrays). Ce type de composant est programmable et permet de concevoir un circuit numérique simplement en programmant des cellules mémoires qui définissent sa fonctionnalité. Un FPGA est principalement constitué de cellules mémoires. C'est pourquoi elles déterminent en grande partie ses caractéristiques comme sa surface ou sa consommation et influencent ses performances comme sa rapidité. Les mémoires MRAM sont composées de Jonctions Tunnel Magnétiques (JTMs) qui stockent l'information sous la forme d'une aimantation. Une JTM est composée de trois couches : deux couches de matériaux ferromagnétiques séparées par une couche isolante. Une des deux couches ferromagnétiques a une aimantation fixée dans un certaine direction (couche de référence) tandis que l'autre peut voir son aimantation changer dans deux directions (couche de stockage). Ainsi, la propagation des électrons est changée suivant que les deux aimantations sont parallèles ou antiparallèles c'est-à-dire que la résistance électrique de la jonction change suivant l'orientation relative des aimantations. Elle est faible lorsque les aimantations sont parallèles et forte lorsqu'elles sont antiparallèles. L'écriture d'une JTM consiste donc à changer l'orientation de l'aimantation de la couche de stockage tandis que la lecture consiste à déterminer si l'on a une forte ou une faible résistance. Les atouts de la JTM font d'elle une bonne candidate pour être une mémoire dite universelle, bien que des efforts de recherche restent à accomplir. Cependant, elle a de nombreux avantages comme la non-volatilité, la rapidité et la faible consommation à l'écriture comparée à la mémoire Flash ainsi que la résistance aux radiations. Grâce à ces avantages, on peut déjà l'utiliser dans certaines applications et en particulier dans le domaine du spatial. En effet, l'utilisation dans ce domaine permet de tirer parti de tous les avantages de la JTM en raison du fait qu'elle est intrinsèquement immune aux radiations et non-volatile. Elle permet donc de réaliser un FPGA résistant aux radiations et avec une basse consommation et de nouvelles fonctionnalités. Le travail de la thèse s'est donc déroulé sur trois ans. La première année a d'abord été dédiée à l'état de l'art afin d'apprendre le fonctionnement des JTMs, l'architecture des FPGAs, les techniques de durcissement aux radiations et de basse consommation ainsi que le fonctionnement des outils utilisés en microélectronique. Au bout de la première année, un nouveau concept d'architecture de FPGA a été proposé. Les deuxième et troisième années ont été dédiées à la réalisation de cette innovation avec la recherche de la meilleure structure de circuit et la réalisation d'un circuit de base d'un FPGA ainsi que la conception puis la fabrication d'un démonstrateur. Le démonstrateur a été testé avec succès et a permis de prouver le concept. La nouvelle architecture de circuit de FPGA a permis de montrer que l'utilisation des mémoires MRAM comme mémoire de configuration de FPGA était avantageuse et en particulier pour les technologies futures.The aim of the thesis was to show that MRAM memory has many advantages for use as a configuration memory for reconfigurable architectures and especially Field Programmable Gate-Arrays (FPGAs). This type of component is programmable and allows designing a digital circuit simply by programming memory cells that define its functionality. An FPGA is thus mainly composed of memory cells. That is why they largely determine its characteristics as its surface or power consumption and affect its performance as its speed. MRAM memories are composed of Magnetic Tunnel Junctions (JTMs) which store information in the form of a magnetization. A JTM is composed of three layers: two layers of ferromagnetic material separated by an insulating layer. One of the two ferromagnetic layers has a magnetization pinned in a fixed direction (reference layer) while the other one can have its magnetization switched between two directions (storage layer). Thus, the propagation of the electrons is changed depending on whether the two magnetizations are parallel or antiparallel that is to say that the electrical resistance of the junction changes according to the orientation of the magnetizations. It is low when the magnetizations are parallel and high when antiparallel. Writing a JTM consists in changing the orientation of the magnetization of the storage layer while reading consists in determining if the resistance is high or low. The advantages of the JTM make it a good candidate to be used as a universal memory although research efforts are still needed. However, it has many advantages such as non-volatility, fast and low power consumption compared to writing to Flash memory as well as resistance to radiation. With these advantages, we may already use it in some applications and in particular in the field of space. Indeed, its use in this area allows taking advantage of all of the benefits of JTM due to the fact that it is intrinsically immune to radiation and non-volatile. It therefore enables to make a radiation hardened and low power FPGA with new functionalities. The work of this thesis is held over three years. The first year was dedicated to the state of the art in order to learn the mechanisms of JTMs, the architecture of FPGAs, radiation hardening and low power consumption techniques as well as the operation of the tools used in microelectronics. After the first year, a new FPGA architecture concept was proposed. The second and third years were devoted to the realization of this innovation with the search for the best circuit structure and the realization of an elementary component of a FPGA and the design and manufacture of a demonstrator. The demonstrator has been successfully tested and proved the new concept. The new circuit architecture of FPGA has shown that the use of MRAM cells as configuration memories for FPGAs was particularly advantageous for future technologies.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

MRAM-Based FPGAs: A Survey

Over the last decade, field programmable gate arrays (FPGAs) have embraced heterogeneity in a transformative way by leveraging emerging memory devices along with conventional CMOS-based devices to realize technology-specific benefits. Memristive device technologies exhibit desirable characteristics such as non-volatility, scalability, near-zero leakage, radiation hardness, and more, making them promising alternatives for SRAM cells found in conventional SRAM-based FPGAs. In recent years, a significant amount of research has been performed to take advantage of these emerging technologies to develop fundamental building blocks of FPGAs like hybrid CMOS-memristive look-up tables (LUTs) and configurable logic blocks (CLBs). In this chapter, we will provide a brief overview of the previous work on hybrid CMOS-memristive FPGAs and their corresponding opportunities and challenges

Conception innovante et développement d'outils de conception d'ASIC pour Technologie Hybride CMOS / Magnétique

Depuis plusieurs années de nombreuses technologies non volatiles sont apparues et ont pris place principalement dans le monde de la mémoire, tendant à remplacer tout type de mémoire. Leurs atouts laissent à penser que certaines d'entre elles, et en particulier les technologies MRAM, pourraient améliorer les performances des circuits intégrés en utilisant leurs composants magnétiques, si connus notamment sous le nom de jonctions tunnel magnétiques, dans la logique. Pour évaluer ces éventuels gains, il faut être capable de concevoir de tels circuits. C'est pourquoi nous proposons dans ces travaux d'une part un kit de conception complet pour les flots de conception full custom et numérique, permettant de couvrir l'ensemble des étapes de conception pour chacun d'entre eux. Une partie de ce kit a servi à plusieurs partenaires de projets de recherche ANR, pour concevoir des démonstrateurs. Nous proposons également dans ce kit de conception un latch magnétique non volatil innovant ultra compact, pour lequel deux brevets d'invention ont été déposés, intégré à une flip-flop. Enfin, nous présentons l'intégration de composants magnétiques à deux applications, sécurité et faible consommation, ainsi qu'une étude qui montre que les gains en consommation statique peuvent être considérables.For several years many non-volatile technologies have been appearing and taking place mainly in the memory world, aiming at replacing all kind of memory. Their assets let thinking that some of them, specially the MRAM technologies, could improve the integrated circuit performances, using their so called magnetic components in the logic, in particular the magnetic tunnel junctions. To evaluate the potential benefits, it is necessary to be able to design such a circuit. That is the reason why we are proposing a full design kit for both full custom and digital designs, allowing all the design steps. Part of this kit has been used by partners in research project to design demonstrators. We also propose in this kit an innovative ultra-compact magnetic latch, for which 2 patents have been deposited, integrated in a flip-flop. Finally, we present the integration of magnetic components for two applications, security and low power, as well as a case study which shows that the static consumption reduction can be huge.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Heterogeneous Reconfigurable Fabrics for In-circuit Training and Evaluation of Neuromorphic Architectures

A heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over fabrics having LUTs constructed with either individual technology alone. Herein, a hierarchical top-down design approach is used to develop the HSCFPGA starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication paradigms. This facilitates a novel architectural approach to reduce leakage energy, minimize communication occurrence and energy cost by eliminating unnecessary data transfer, and support auto-tuning for resilience. Furthermore, HSC-FPGA enables new advantages of technology co-design which trades off alternative mappings between emerging devices and transistors at runtime by allowing dynamic remapping to adaptively leverage the intrinsic computing features of each device technology. HSC-FPGA offers a platform for fine-grained Logic-In-Memory architectures and runtime adaptive hardware. An orthogonal dimension of fabric heterogeneity is also non-determinism enabled by either low-voltage CMOS or probabilistic emerging devices. It can be realized using probabilistic devices within a reconfigurable network to blend deterministic and probabilistic computational models. Herein, consider the probabilistic spin logic p-bit device as a fabric element comprising a crossbar-structured weighted array. The Programmability of the resistive network interconnecting p-bit devices can be achieved by modifying the resistive states of the array\u27s weighted connections. Thus, the programmable weighted array forms a CLB-scale macro co-processing element with bitstream programmability. This allows field programmability for a wide range of classification problems and recognition tasks to allow fluid mappings of probabilistic and deterministic computing approaches. In particular, a Deep Belief Network (DBN) is implemented in the field using recurrent layers of co-processing elements to form an n x m1 x m2 x ::: x mi weighted array as a configurable hardware circuit with an n-input layer followed by i ≥ 1 hidden layers. As neuromorphic architectures using post-CMOS devices increase in capability and network size, the utility and benefits of reconfigurable fabrics of neuromorphic modules can be anticipated to continue to accelerate

Energy and Area Efficient Machine Learning Architectures using Spin-Based Neurons

Recently, spintronic devices with low energy barrier nanomagnets such as spin orbit torque-Magnetic Tunnel Junctions (SOT-MTJs) and embedded magnetoresistive random access memory (MRAM) devices are being leveraged as a natural building block to provide probabilistic sigmoidal activation functions for RBMs. In this dissertation research, we use the Probabilistic Inference Network Simulator (PIN-Sim) to realize a circuit-level implementation of deep belief networks (DBNs) using memristive crossbars as weighted connections and embedded MRAM-based neurons as activation functions. Herein, a probabilistic interpolation recoder (PIR) circuit is developed for DBNs with probabilistic spin logic (p-bit)-based neurons to interpolate the probabilistic output of the neurons in the last hidden layer which are representing different output classes. Moreover, the impact of reducing the Magnetic Tunnel Junction\u27s (MTJ\u27s) energy barrier is assessed and optimized for the resulting stochasticity present in the learning system. In p-bit based DBNs, different defects such as variation of the nanomagnet thickness can undermine functionality by decreasing the fluctuation speed of the p-bit realized using a nanomagnet. A method is developed and refined to control the fluctuation frequency of the output of a p-bit device by employing a feedback mechanism. The feedback can alleviate this process variation sensitivity of p-bit based DBNs. This compact and low complexity method which is presented by introducing the self-compensating circuit can alleviate the influences of process variation in fabrication and practical implementation. Furthermore, this research presents an innovative image recognition technique for MNIST dataset on the basis of p-bit-based DBNs and TSK rule-based fuzzy systems. The proposed DBN-fuzzy system is introduced to benefit from low energy and area consumption of p-bit-based DBNs and high accuracy of TSK rule-based fuzzy systems. This system initially recognizes the top results through the p-bit-based DBN and then, the fuzzy system is employed to attain the top-1 recognition results from the obtained top outputs. Simulation results exhibit that a DBN-Fuzzy neural network not only has lower energy and area consumption than bigger DBN topologies while also achieving higher accuracy

Utilizing Magnetic Tunnel Junction Devices in Digital Systems

The research described in this dissertation is motivated by the desire to effectively utilize magnetic tunnel junctions (MTJs) in digital systems. We explore two aspects of this: (1) a read circuit useful for global clocking and magnetologic, and (2) hardware virtualization that utilizes the deeply-pipelined nature of magnetologic. In the first aspect, a read circuit is used to sense the state of an MTJ (low or high resistance) and produce a logic output that represents this state. With global clocking, an external magnetic field combined with on-chip MTJs is used as an alternative mechanism for distributing the clock signal across the chip. With magnetologic, logic is evaluated with MTJs that must be sensed by a read circuit and used to drive downstream logic. For these two uses, we develop a resistance-to-voltage (R2V) read circuit to sense MTJ resistance and produce a logic voltage output. We design and fabricate a prototype test chip in the 3 metal 2 poly 0.5 um process for testing the R2V read circuit and experimentally validating its correctness. Using a clocked low/high resistor pair, we show that the read circuit can correctly detect the input resistance and produce the desired square wave output. The read circuit speed is measured to operate correctly up to 48 MHz. The input node is relatively insensitive to node capacitance and can handle up to 10s of pF of capacitance without changing the bandwidth of the circuit. In the second aspect, hardware virtualization is a technique by which deeply-pipelined circuits that have feedback can be utilized. MTJs have the potential to act as state in a magnetologic circuit which may result in a deep pipeline. Streams of computation are then context switched into the hardware logic, allowing them to share hardware resources and more fully utilize the pipeline stages of the logic. While applicable to magnetologic using MTJs, virtualization is also applicable to traditional logic technologies like CMOS. Our investigation targets MTJs, FPGAs, and ASICs. We develop M/D/1 and M/G/1 queueing models of the performance of virtualized hardware with secondary memory using a fixed, hierarchical, round-robin schedule that predict average throughput, latency, and queue occupancy in the system. We develop three C-slow applications and calibrate them to a clock and resource model for FPGA and ASIC technologies. Last, using the M/G/1 model, we predict throughput, latency, and resource usage for MTJ, FPGA, and ASIC technologies. We show three design scenarios illustrating ways in which to use the model