A high-Tc 4-bit periodic threshold analog-to-digital converter

Using ramp-type Josephson junctions a 4-bit periodic threshold ADC has been designed, fabricated and tested. Practical design constraints will be discussed in terms of noise immunity, flux flow, available technology, switching speed etc. In a period of four years we fabricated about 100 chips in order to bring the technology to an acceptable level and to test various designs and circuit layouts. This resulted in a basic comparator that is rather insensitive to the stray field generated by the analog input signal or variations in mask alignment during fabrication. The input signal is fed into the comparators using a resistive divider network. Full functionality at low frequencies has been demonstrate

An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier

Comparators are one of the most fundamental building blocks in all electronic systems involving analog and digital information. A comparator’s performance, or the accuracy of its output, is determined by the comparator’s offset voltage, which includes random offset and systematic offset. To guarantee the overall performance of an entire electronic system, offset-trimming techniques are often necessary to reduce inaccuracy. This study analyzes the offset errors in a representative comparator structure and describes an auto-calibration technique to systematically and significantly reducing the offset. The auto-calibration technique involves trimming of the comparator input transistor pair. Various trimming-switch structures are considered and compared, such as constant-sized drain switch (CDS), constant-sized gate switch (CGS), constant-sized source switch (CSS), binary-weighted source switch (BSS), and constant size split-source switch (SSS). The comparator and the offset auto-calibration circuits are designed using the GlobalFoundry 0.13μm process. Then an offset trimming algorithm, which is written on MATLAB, is applied to these circuits. Afterwards, the results are collected and analyzed. A comparison of linearity and trimming range (TR) achieved with different trimming switch structures is performed to demonstrate advantages and disadvantages of each switch scheme. The results are also plotted in a histogram to show the normal distribution of each scheme. Finally, offset cancellation technique is implemented in an operational amplifier (Op Amp) circuit with further analysis and comparison to prove the methodology

Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital converters

Different aspects of power optimization of a high-speed, high-accuracy pipeline Analog-to-Digital Converters (ADCs) are considered to satisfy the current and future needs of portable communication devices. First power optimized design strategies for the amplifiers are introduced. Closed form expressions of power w.r.t settling requirements are presented to facilitate a fair comparison and selection of the amplifier structure. Next a new low offset dynamic comparator has been designed. Simulation based sensitivity analysis is performed to demonstrate the robustness of the new comparator with respect to stray capacitances, common mode voltage errors and timing errors. With simplified amplifier power model along with the use of dynamic comparators, a method to optimize the power consumption of a pipeline ADC with kT/C noise constraint is also developed. The total power dependence on capacitor scaling and stage resolution is investigated for a near-optimal solution.;After considering the power requirements of a pipeline ADC, design and statistical modeling of over-range protection requirements is investigated. Closed form statistical expressions for the over-range requirements are developed to assist in the allocation of the error budgets to different pipeline blocks. A new over-range protection algorithm is also developed that relaxes the amplifier design and power requirements.;Finally, two new CMOS Schmitt trigger designs are proposed which can be used as clock inputs for the pipeline ADC. In the new designs, sizing of the feedback inverters is used for independent trip point control. The new designs have also a modest reduction in sensitivity to process variations along with immunity to the kick-back noise without the addition of path delay

Neuro-fuzzy chip to handle complex tasks with analog performance

This paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input–output delay, and precision, performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called multiplexing fuzzy controller (MFCON), has been realized in a CMOS 0.7 um standard technology. It has two inputs, implements 64 rules, and features 500 ns of input to output delay with 16-mW of power consumption. Results from the chip in a control application with a dc motor are also provided

Neuro-fuzzy chip to handle complex tasks with analog performance

This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay and precision performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core [1]. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called MFCON, has been realized in a CMOS 0.7μm standard technology. It has two inputs, implements 64 rules and features 500ns of input to output delay with 16mW of power consumption. Results from the chip in a control application with a DC motor are also provided

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consumption is 70 mW from a 1.2-V supply voltage when is clocked at 240MHz. CADENCE-SPECTRE simulations show 12-bit effective resolution within a 20-MHz signal bandwidth.This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.Peer reviewe

Improvements the direct torque control performance for an induction machine using fuzzy logic controller

This article examines a solution to the major problems of induction machine control in order to achieve superior dynamic performance. Conventional direct torque control and indirect control with flux orientation have some drawbacks, such as current harmonics, torque ripples, flux ripples, and rise time. In this article, we propose a comparative analysis between previous approaches and the one using fuzzy logic. Results from the simulation show that the direct torque control method using fuzzy logic is more effective in providing a precise and fast response without overshooting, and it eliminates torque and flux fluctuations at low switching frequencies. The demonstrated improvements in dynamic performance contribute to increased operational efficiency and reliability in industrial applications

A multiplexed mixed-signal fuzzy architecture

Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, imposes a limit of complexity, hence fuzzy analog controllers are usually oriented to fast low-power systems with low-medium complexity. The paper presents a strategy to preserve most of the advantages of an analog implementation, while allowing a notorious increment of the system complexity. Such strategy consists in implementing a reduced number of rules, those that really determine the output in a lattice controller, which we call analog core, then this core is dynamically programmed to perform the computation related to a specific rule set. The data to program the analog core are stored in a memory, and constitutes the whole knowledge base in a kind of virtual rule set. HSPICE simulations from an exemplary controller are shown to illustrate the viability of the proposal

Fuzzy-based estimation of reference flux, reference torque and sector rotation for performance improvement of DTC-IM drive

In this study, the fuzzy-based reference flux estimator (RFE), reference torque estimator (RTE) and sector rotation strategy called fuzzy logic estimator are proposed to direct torque control of induction motor (DTC-IM) drive for performance improvement. The basic DTC-IM drive with conventional RFE, RTE and sector division causes large torque ripple, variable switching frequency and uneven voltage vector contribution in stator flux. The torque and speed responses of the proposed system are investigated with load variations. The simulation results of the proposed DTC-IM drive are compared with the basic DTC-IM drive. The assessment of the proposed system shows improved performance. A hardware is developed using Xilinx Spartan-6XC6SLX45-Field Programmable Gate Array (FPGA) Kit for experimental verification of the results. Moreover, sinusoidal pulse width modulation and space vector pulse width modulation techniques are applied to reduce the torque ripples. The performance of the drive is investigated for various speed ranges. The comparison of the simulated and experimental results proves that the proposed fuzzy-based DTC-IM drive provides better performance than the basic DTC-IM drive