Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Calibration techniques in nyquist A/D converters

In modern systems signal processing is performed in the digital domain. Contrary to analog circuits, digital signal processing offers more robustness, programmability, error correction and storage possibility. The trend to shift the A/D converter towards the input of the system requires A/D converters with more dynamic range and higher sampling speeds. This puts extreme demands on the A/D converter and potentially increases the power consumption. Calibration Techniques in Nyquist A/D Converters analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It is shown that in order to achieve high speed and high accuracy at high power efficiency, calibration is required. Calibration reduces the overall power consumption by using the available digital processing capability to relax the demands on critical power hungry analog components. Several calibration techniques are analyzed. The calibration techniques presented in this book are applicable to other analog-to-digital systems, such as those applied in integrated receivers. Further refinements will allow using analog components with less accuracy, which will then be compensated by digital signal processing. The presented methods allow implementing this without introducing a speed or power penalty

Development of a two-dimensional virtual pixel X-ray imaging detector for time-resolved structure research

An interpolating two-dimensional X-ray imaging detector based on a single photon counter with gas amplification by GEM (gas electron multiplier) structures is presented. The detector system can be used for time-resolved structure research down to the microsecond-time domain. The prototype detector has been tested at the SAXS beamline at ELETTRA synchrotron light source with a beam energy of 8 keV to test its capabilities in the rough beamline environment. The imaging performance is examined with apertures and standard diffraction targets. Finally, the application in a time-resolved lipid temperature jump experiment is presented.Comment: 10 pages, 14 figures, accepted for publication in J. Synchrotron Rad, revised version, paper shortened, minor change

A 0.2pJ/conversion-step 6-bit 200MHz flash ADC with redundancy

Comunicación presentada al "27th Conference on Design of Circuits and Integrated Systems (DCIS 2012)" celebrada del 28 al 30 de Noviembre del 2012 en Avignon (Francia), organizada por el LIRMM laboratory of Montpellier: http://www.lirmm.fr/dcis2012/index.phpIn this paper, a 200MHz 6-bit Flash analog-to-digital converter (ADC) is presented. The principal objective is to obtain a digital-friendly converter. Hence, small and simple latched comparators are used and redundancy allows reducing the offset down to an acceptable level. This obviously requires calibration but reduces power consumption, since small size transistors can be used and the unused comparators are powered down. The proposed ADC is designed in UMC 0:18m CMOS technology. Full electrical simulations show that the ADC reaches an effective number of bits (ENOB) of 5.3 associated to a signal-to-noise-anddistortion ratio (SNDR) is 33dB. The converter consumes only 1.56mW and has figure-of-merit (FoM) of 0.2 pJ / conversion step.This work has been partially funded by the Junta de Andalucia project P09-TIC-5386, the Ministerio de Economia y Competitividad project TEC2011-28302, both of them cofinanced by the FEDER program.Peer Reviewe

High-Speed Analog-to-Digital Converters for Broadband Applications

Flash Analog-to-Digital Converters (ADCs), targeting optical communication standards, have been reported in SiGe BiCMOS technology. CMOS implementation of such designs faces two challenges. The first is to achieve a high sampling speed, given the lower gain-bandwidth (lower ft) of CMOS technology. The second challenge is to handle the wide bandwidth of the input signal with a certain accuracy. Although the first problem can be relaxed by using the time-interleaved architecture, the second problem remains as a main obstacle to CMOS implementation. As a result, the feasibility of the CMOS implementation of ADCs for such applications, or other wide band applications, depends primarily on achieving a very small input capacitance (large bandwidth) at the desired accuracy. In the flash architecture, the input capacitance is traded off for the achievable accuracy. This tradeoff becomes tighter with technology scaling. An effective way to ease this tradeoff is to use resistive offset averaging. This permits the use of smaller area transistors, leading to a reduction in the ADC input capacitance. In addition, interpolation can be used to decrease the input capacitance of flash ADCs. In an interpolating architecture, the number of ADC input preamplifiers is reduced significantly, and a resistor network interpolates the missing zero-crossings needed for an N-bit conversion. The resistive network also averages out the preamplifiers offsets. Consequently, an interpolating network works also as an averaging network. The resistor network used for averaging or interpolation causes a systematic non-linearity at the ADC transfer characteristics edges. The common solution to this problem is to extend the preamplifiers array beyond the input signal voltage range by using dummy preamplifiers. However, this demands a corresponding extension of the flash ADC reference-voltage resistor ladder. Since the voltage headroom of the reference ladder is considered to be a main bottleneck in the implementation of flash ADCs in deep-submicron technologies with reduced supply voltage, extending the reference voltage beyond the input voltage range is highly undesirable. The principal objective of this thesis is to develop a new circuit technique to enhance the bandwidth-accuracy product of flash ADCs. Thus, first, a rigorous analysis of flash ADC architectures accuracy-bandwidth tradeoff is presented. It is demonstrated that the interpolating architecture achieves a superior accuracy compared to that of a full flash architecture for the same input capacitance, and hence would lead to a higher bandwidth-accuracy product, especially in deep-submicron technologies that use low power supplies. Also, the gain obtained, when interpolation is employed, is quantified. In addition, the limitations of a previous claim, which suggests that an interpolating architecture is equivalent to an averaging full flash architecture that trades off accuracy for the input capacitance, is presented. Secondly, a termination technique for the averaging/interpolation network of flash ADC preamplifiers is devised. The proposed technique maintains the linearity of the ADC at the transfer characteristics edges and cancels out the over-range voltage, consumed by the dummy preamplifiers. This makes flash ADCs more amenable for integration in deep-submicron CMOS technologies. In addition, the elimination of this over-range voltage allows a larger least-significant bit. As a result, a higher input referred offset is tolerated, and a significant reductions in the ADC input capacitance and power dissipation are achieved at the same accuracy. Unlike a previous solution, the proposed technique does not introduce negative transconductance at flash ADC preamplifiers array edges. As a result, the offset averaging technique can be used efficiently. To prove the resulting saving in the ADC input capacitance and power dissipation that is attained by the proposed termination technique, a 6-bit 1.6-GS/s flash ADC test chip is designed and implemented in 0.13-$\mu$m CMOS technology. The ADC consumes 180 mW from a 1.5-V supply and achieves a Signal-to-Noise-plus-Distortion Ratio (SNDR) of 34.5 dB and 30 dB at 50-MHz and 1450-MHz input signal frequency, respectively. The measured peak Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL) are 0.42 LSB and 0.49 LSB, respectively

Sampled charge reuse for power reduction in switched capacitor data converters

Advances in semiconductor fabrication have enabled the shrinking of digital systems dramatically over the years. Although digital circuitry benefits tremendously from the constant shrinking of the device sizes, the benefits for analog circuits are not quite so dramatic. Low power is of critical importance in all mobile devices. Any reduction in power in the embedded analog-to-digital converters (ADCs) in such devices can help prolong the battery life. A technique is proposed that can be used to reduce power dissipation in ADCs that use switched-capacitor gain stages. It is shown for a pipeline ADC that the signal charge stored across the feedback capacitor from the first stage can be reused in the second stage at the end of the first stage\u27s amplify phase. The extra overhead of an extra capacitor is justified by the power savings of the proposed scheme;A well known approach for reducing the power dissipation in pipelined ADCs is the scaling down of capacitors progressively down the pipeline stream. The proposed technique combines the scaling of the capacitors with charge reuse. This combination inherits the power saving benefits of capacitor scaling and adds to the power saving by sharing the capacitor in two consecutive stages. Due to the highest power budget allocated to the first two stages, the sharing 2 is limited to the first two stages. Additionally, it is shown that the charge reuse results in reducing the total capacitive load driven by a stage\u27s opamp, potentially reducing the current requirements of the opamp;The proposed technique has been adapted for use in cyclic ADCs. The proposed technique reuses the charge from the first cycle in the next. This approach helps to reduce the die area of the capacitors in the switched capacitor network by up to 50%. Consequently, the power consumption requirement of the operational amplifier can be reduced. This is achieved while maintaining the thermal noise performance and conversion rate of the conventional structure. A 10-bit, 2.3MHz cyclic ADC using the new structure is implemented in 0.5mum CMOS. Spectre simulation results show a THD of -76dB and SFDR of -74.95dB

High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip

With higher-level integration driven by increasingly complex digital systems and downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging technology of low power, high cost effectiveness and high reliability and is exceedingly attractive for applications in high-speed data conversion wireless and wideband communication systems. This research presents a novel ADC comparator design methodology; the speed and performance of which is not restricted by the supply voltage reduction and device linearity deterioration in scaling-down CMOS processes. By developing a dynamic offset suppression technique and a circuit optimization method, the comparator can achieve a 3 dB frequency of 2 GHz in 130 nanometer (nm) CMOS process. Combining this new comparator design and a proposed pipelined thermometer-Gray- binary encoder designed by the DCVSPG logic, a high-speed, low-voltage clocked-digital- comparator (CDC) pipelined CMOS flash ADC architecture is proposed for wideband communication SoC. This architecture has advantages of small silicon area, low power, and low cost. Three CDC-based pipelined CMOS flash ADCs were implemented in 130 nm CMOS process and their experimental results are reported: 1. 4-b, 2.5-GSPS ADC: SFDR of 21.48-dB, SNDR of 15.99-dB, ENOB of 2.4-b, ERBW of 1-GHz, power of 7.9-mW, and area of 0.022-mm2. 2. 4-b, 4-GSPS ADC: SFDR of 25-dB, SNDR of 18.6-dB, ENOB of 2.8-b, ERBW of 2-GHz, power of 11-mW. 3. 6-b, 4-GSPS ADC: SFDR of 48-dB at a signal frequency of 11.72-MHz, SNDR of 34.43-dB, ENOB of 5.4-b, power of 28-mW. An application of the proposed CDC-based pipelined CMOS flash ADC is 1-GHz bandwidth, 2.5-GSPS digital receiver on a chip. To verify the performance of the receiver, a mixed-signal block-level simulation and verification flow was built in Cadence AMS integrated platform. The verification results of the digital receiver using a 4-b 2.5-GSPS CDC-based pipelined CMOS ADC, a 256-point, 12-point kernel function FFT and a frequency detection logic show that two tone signals up to 1125 MHz can be detected and discriminated. A notable contribution of this research is that the proposed ADC architecture and the comparator design with dynamic offset suppression and optimization are extremely suitable for future VDSM CMOS processes and make all-digital receiver SoC design practical