Performance Comparison of Static CMOS and Domino Logic Style in VLSI Design: A Review

Of late, there is a steep rise in the usage of handheld gadgets and high speed applications. VLSI designers often choose static CMOS logic style for low power applications. This logic style provides low power dissipation and is free from signal noise integrity issues. However, designs based on this logic style often are slow and cannot be used in high performance circuits. On the other hand designs based on Domino logic style yield high performance and occupy less area. Yet, they have more power dissipation compared to their static CMOS counterparts. As a practice, designers during circuit synthesis, mix more than one logic style judiciously to obtain the advantages of each logic style. Carefully designing a mixed static Domino CMOS circuit can tap the advantages of both static and Domino logic styles overcoming their own short comings

Powertrain Architectures and Technologies for New Emission and Fuel Consumption Standards

New powertrain design is highly influenced by CO2 and pollutant limits defined by legislations, the demand of fuel economy in for real conditions, high performances and acceptable cost. To reach the requirements coming from both end-users and legislations, several powertrain architectures and engine technologies are possible (e.g. SI or CI engines), with many new technologies, new fuels, and different degree of electrification. The benefits and costs given by the possible architectures and technology mix must be accurately evaluated by means of objective procedures and tools in order to choose among the best alternatives. This work presents a basic design methodology and a comparison at concept level of the main powertrain architectures and technologies that are currently being developed, considering technical benefits and their cost effectiveness. The analysis is carried out on the basis of studies from the technical literature, integrating missing data with evaluations performed by means of powertrain-vehicle simplified models, considering the most important powertrain architectures. Technology pathways for passenger cars up to 2025 and beyond have been defined. After that, with support of more detailed models and experimentations, the investigation has been focused on the more promising technologies to improve internal combustion engine, such as: water injection, low temperature combustions and heat recovery systems

Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares

Pass Transistor Logic (PTL) is a well known approach for implementing digital circuits. In order to handle larger designs and also to ensure that the total number of series devices in the resulting circuit is bounded, partitioned Reduced Ordered Binary Decision Diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each partitioned block typically needs to be buffered. In this thesis, a new methodology is presented to perform generalized buffering of the outputs of PTL blocks. By performing the Boolean division of each PTL block using different gates in a library, we select the gate that results in the largest reduction in the height of the PTL block. In this manner, these gates serve the function of buffering the outputs of the PTL blocks, while also reducing the height and delay of the PTL block. PTL synthesis with generalized buffering was implemented in two different ways. In the first approach, Boolean division was used to perform generalized buffering. In the second approach, compatible observability don't cares (CODCs) were utilized in tandem with Boolean division to simplify the ROBDDs and to reduce the logic in PTL structure. Also CODCs were computed in two different manners: one using full simplify to compute complete CODCs and another using, approximate CODCs (ACODCs). Over a number of examples, on an average, generalized buffering without CODCs results in a 24% reduction in delay, and a 3% improvement in circuit area, compared to a traditional buffered PTL implementation. When ACODCs were used, the delay was reduced by 29%, and the total area was reduced by 5% compared to traditional buffering. With complete CODCs, the delay and area reduction compared to traditional buffering was 28% and 6% respectively. Therefore, results show that generalized buffering provides better implementation of the circuits than the traditional buffering method

Implementation of arithmetic primitives using truly deep submicron technology (TDST)

The invention of the transistor in 1947 at Bell Laboratories revolutionised the electronics industry and created a powerful platform for emergence of new industries. The quest to increase the number of devices per chip over the last four decades has resulted in rapid transition from Small-Scale-Integration (SSI) and Large-Scale-lntegration (LSI), through to the Very-Large-Scale-Integration (VLSI) technologies, incorporating approximately 10 to 100 million devices per chip. The next phase in this evolution is the Ultra-Large-Scale-Integration (ULSI) aiming to realise new application domains currently not accessible to CMOS technology. Although technology is continuously evolving to produce smaller systems with minimised power dissipation, the IC industry is facing major challenges due to constraints on power density (W/cm2) and high dynamic (operating) and static (standby) power dissipation. Mobile multimedia communication and optical based technologies have rapidly become a significant area of research and development challenging a variety of technological fronts. The future emergence or 4G (4th Generation) wireless communications networks is further driving this development, requiring increasing levels of media rich content. The processing requirements for capture, conversion, compression, decompression, enhancement and display of higher quality multimedia, place heavy demands on current ULSI systems. This is also apparent for mobile applications and intelligent optical networks where silicon chip area and power dissipation become primary considerations. In addition to the requirements for very low power, compact size and real-time processing, the rapidly evolving nature of telecommunication networks means that flexible soft programmable systems capable of adaptation to support a number of different standards and/or roles become highly desirable. In order to fully realise the capabilities promised by the 4G and supporting intelligent networks, new enabling technologies arc needed to facilitate the next generation of personal communications devices. Most of the current solutions to meet these challenges are based on various implementations of conventional architectures. For decades, silicon has been the main platform of computing, however it is slow, bulky, runs too hot, and is too expensive. Thus, new approaches to architectures, driving multimedia and future telecommunications systems, are needed in order to extend the life cycle of silicon technology. The emergence of Truly Deep Submicron Technology (TDST) and related 3-D interconnection technologies have provided potential alternatives from conventional architectures to 3-D system solutions, through integration of IDST, Vertical Software Mapping and Intelligent Interconnect Technology (IIT). The concept of Soft-Chip Technology (SCT) entails integration of Soft• Processing Circuits with Soft-Configurable Circuits . This concept can effectively manipulate hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design algorithm for content-rich multimedia, telecommunication and intelligent networking system applications. 3•D architectures (design algorithms used suitable for 3-D soft-chip technology), are driven by three factors. The first is development of new device technology (TDST) that can support new architectures with complexities of 100M to 1000M devices. The second is development of advanced wafer bonding techniques such as Indium bump and the more futuristic optical interconnects for 3-D soft-chip mapping. The third is related to improving the performance of silicon CMOS systems as devices continue to scale down in dimensions. One of the fundamental building blocks of any computer system is the arithmetic component. Optimum performance of the system is determined by the efficiency of each individual component, as well as the network as a whole entity. Development of configurable arithmetic primitives is the fundamental focus in 3-D architecture design where functionality can be implemented through soft configurable hardware elements. Therefore the ability to improve the performance capability of a system is of crucial importance for a successful design. Important factors that predict the efficiency of such arithmetic components are: • The propagation delay of the circuit, caused by the gate, diffusion and wire capacitances within !he circuit, minimised through transistor sizing. and • Power dissipation, which is generally based on node transition activity. [2] Although optimum performance of 3-D soft-chip systems is primarily established by the choice of basic primitives such as adders and multipliers, the interconnecting network also has significant degree of influence on !he efficiency of the system. 3-D superposition of devices can decrease interconnect delays by up to 60% compared to a similar planar architecture. This research is based on development and implementation of configurable arithmetic primitives, suitable to the 3-D architecture, and has these foci: • To develop a variety of arithmetic components such as adders and multipliers with particular emphasis on minimum area and compatible with 3-D soft-chip design paradigm. • To explore implementation of configurable distributed primitives for arithmetic processing. This entails optimisation of basic primitives, and using them as part of array processing. In this research the detailed designs of configurable arithmetic primitives are implemented using TDST O.l3µm (130nm) technology, utilising CAD software such as Mentor Graphics and Cadence in Custom design mode, carrying through design, simulation and verification steps

Analysis of Various DCVSL Structures and Implementation of Full Adder with Them

The Differential Cascode Voltage Switch Logic (DCVSL) is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of power dissipation, circuit delay, layout density and logic flexibility. In this paper, a detailed comparison of all the DCVSL structures are provided including the implementation of Full Adder circuit with the help of those DCVSL structures, which includes Static DCVSL, Dynamic DCVSL and Modified DCVSL. The performance analysis is done in Cadence Virtuoso 90nm CMOS Technology. The working of these DCVSL structures is based on the concept of ‘Multiplexer’. A multiplexer also known as ‘mux’, which is a device where from a number of input signals, selection is done. It is basically a combinational logic circuit. The multiplexer is a unidirectional device, which is used in applications where a data must be switched from multiple sources to a destination. The analysis of all these DCVSL structures is followed by the implementation of Full Adder. Adders are the building blocks in computer systems. Digital Computer Systems widely uses Arithmetic operations. Addition is a necessary arithmetic operation, which is also the root for arithmetic operation such as multiplication. Similarly, adding another XOR gate, the basic adder cell can be modified to function as subtractor, which can be used for division. Therefore, 1-bit Full Adder cell is the ultimate and simple block of an arithmetic unit of a system. So, the basic 1-bit Full Adder cell must be improved, so that the performance of the digital circuits. In VLSI, there is always a trade-off between speed and power dissipation. One parameter is improved, the other gets degraded. Hence, the parameter power delay product is introduced. So, to achieve speeds, high drivability hybrid-DCVSL design methodologies are used to build adder cell in this work. The DCVSL gates produces both complementary and true outputs using single gate architecture. And, the multipliers in the design are based on the pass transistor logic (PTL), because these occupies less chip area per component and also are simple to construct. The parameters compared are power dissipation, propagation delay time, power delay product, transistor number and power dissipation (average). The Static DCVSL structure produces best result in terms of power dissipation, delay and power delay product. Whereas, in case of the Adder circuit, the power consumption is best for the Dynamic DCVSL Adder, along with the delay and the power delay product for the output Sum; but for the output Cout, the best option is Static DCVSL Adder, as the delay and the power delay product is least in this case

Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI design necessitate new digital logic techniques and styles that are at the same time high performance, energy efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down network. With continuous technology scaling, this problem is getting more and more severe. In this thesis, a new noise tolerant dynamic CMOS circuit technique is proposed. In the proposed work, we have enhanced the behavior of the domino CMOS logic. This technique also gets benefit in terms of delay and power. This thesis describes the new low power, noise tolerant and high speed domino logic technique and presents a comparison result of this logic with previously reported schemes. Simulation results prove that, in 180 nm CMOS technology when we used this logic style to realize wide fan-in logic gates, it could achieve maximum level of noise robustness as compared to its basic counterpart. In addition, the logic also works efficiently with sequential circuits. The feasibility of this new technique is demonstrated by means of a real hardware, we have built a custom test-chip in the UMC 180 nm process technology with an ALU core, using the proposed domino logic style for each design block. In this thesis, we have also described the design and implementation of this chip. In addition to this, we have also presented initial power and delay performance comparisons between the circuit level simulated ALU and test-chip implemented in the proposed domino logic style. Finally we conclude that, the thesis contributes a very efficient logic style for wide fan-in gates, which is not only noise robust but also energy efficient and high speed

Biomolecular System Design: Architecture, Synthesis, and Simulation

The advancements in systems and synthetic biology have been broadening the range of realizable systems with increasing complexity both in vitro and in vivo. Systems for digital logic operations, signal processing, analog computation, program flow control, as well as those composed of different functions – for example an on-site diagnostic system based on multiple biomarker measurements and signal processing – have been realized successfully. However, the efforts to date tend to tackle each design problem separately, relying on ad hoc strategies rather than providing more general solutions based on a unified and extensible architecture, resulting in long development cycle and rigid systems that require redesign even for small specification changes.Inspired by well-tested techniques adopted in electronics design automation (EDA), this work aims to remedy current design methodology by establishing a standardized, complete flow for realizing biomolecular systems. Given a behavior specification, the flow streamlines all the steps from modeling, synthesis, simulation, to final technology mapping onto implementing chassis. The resulted biomolecular systems of our design flow are all built on top of an FPGA-like reconfigurable architecture with recurring modules. Each module is designed the function of eachmodule depends on the concentrations of assigned auxiliary species acting as the “tuning knobs.” Reconfigurability not only simplifies redesign for altered specification or post-simulation correction, but also makes post-manufacture fine-tuning – even after system deployment – possible. This flexibility is especially important in synthetic biology due to the unavoidable variations in both the deployed biological environment and the biomolecular reactions forming the designed system.In fact, by combining the system’s reconfigurability and neural network’s self-adaptiveness through learning, we further demonstrate the high compatibility of neuromorphic computation to our proposed architecture. Simulation results verified that with each module implementing a neuron of selected model (ex. spike-based, threshold-gate-like, etc.), accompanied by an appropriate choice of reconfigurable properties (ex. threshold value, synaptic weight, etc.), the system built from our proposed flow can indeed perform desired neuromorphic functions

NASA Thesaurus. Volume 2: Access vocabulary

The NASA Thesaurus -- Volume 2, Access Vocabulary -- contains an alphabetical listing of all Thesaurus terms (postable and nonpostable) and permutations of all multiword and pseudo-multiword terms. Also included are Other Words (non-Thesaurus terms) consisting of abbreviations, chemical symbols, etc. The permutations and Other Words provide 'access' to the appropriate postable entries in the Thesaurus