Synthesis for Logical Initializability of Synchronous Finite State Machines

A new method is introduced for the synthesis for logical initializability of synchronous state machines. The goal is to synthesize a gate-level implementation that is initializable when simulated by a 3-valued (0,1,X) simulator. The method builds on an existing approach of Cheng and Agrawal, which uses constrained state assignment to translate functional initializability into logical initializability. Here, a different state assignment method is proposed which, unlike the method of Cheng and Agrawal, is guaranteed safe and yet is not as conservative. Furthermore, it is demonstrated that certain new constraints on combinational logic synthesis are both necessary and sufficient to insure that the resulting gate-level circuit is 3-valued simulatable. Interestingly, these constraints are similar to those used for hazard-free synthesis of asynchronous combinational circuits. Using the above constraints, we present a complete synthesis for initializability method, targeted to both two-level and multi-level circuits

Using formal methods to support testing

Formal methods and testing are two important approaches that assist in the development of high quality software. While traditionally these approaches have been seen as rivals, in recent years a new consensus has developed in which they are seen as complementary. This article reviews the state of the art regarding ways in which the presence of a formal specification can be used to assist testing

Towards Automated Test Sequence Generation

The article presents a novel control-flow based test sequence generation technique using UML 2.0 activity diagram, which is a behavioral type of UML diagram. Like other model-based techniques, this technique can be used in the earlier phases of the development process owing to the availability of the design models of the system. The activity diagram model is seamlessly converted into a colored Petri net. We proposed a technique that enables the automatic generation of test sequences according to a given coverage criteria from the execution of the colored Petri nets model. Two types of structural coverage criteria for AD based models, namely sequential and concurrent coverage are described. The proposed technique was applied to an example to demonstrate its feasibility and the generated test sequences were evaluated against selected coverage criteria. This technique can potentially be adapted to service oriented applications, workflows, and concurrent applications

Decoupling algorithms from schedules for easy optimization of image processing pipelines

Using existing programming tools, writing high-performance image processing code requires sacrificing readability, portability, and modularity. We argue that this is a consequence of conflating what computations define the algorithm, with decisions about storage and the order of computation. We refer to these latter two concerns as the schedule, including choices of tiling, fusion, recomputation vs. storage, vectorization, and parallelism. We propose a representation for feed-forward imaging pipelines that separates the algorithm from its schedule, enabling high-performance without sacrificing code clarity. This decoupling simplifies the algorithm specification: images and intermediate buffers become functions over an infinite integer domain, with no explicit storage or boundary conditions. Imaging pipelines are compositions of functions. Programmers separately specify scheduling strategies for the various functions composing the algorithm, which allows them to efficiently explore different optimizations without changing the algorithmic code. We demonstrate the power of this representation by expressing a range of recent image processing applications in an embedded domain specific language called Halide, and compiling them for ARM, x86, and GPUs. Our compiler targets SIMD units, multiple cores, and complex memory hierarchies. We demonstrate that it can handle algorithms such as a camera raw pipeline, the bilateral grid, fast local Laplacian filtering, and image segmentation. The algorithms expressed in our language are both shorter and faster than state-of-the-art implementations.National Science Foundation (U.S.) (Grant 0964004)National Science Foundation (U.S.) (Grant 0964218)National Science Foundation (U.S.) (Grant 0832997)United States. Dept. of Energy (Award DE-SC0005288)Cognex CorporationAdobe System

Formal development and evaluation of narrow passageway system operations

This study applies a new intelligent transportation methodology for transforming informal operations concepts for narrow passageway systems into system-level designs, which will formal enough to support automated validation of anticipated component- and system-level behaviours. Models and specifications of behaviour are formally designed as labelled transition systems. Each object is the management system is assumed to have behaviour that can be defined by a finite state machine; thus, the waterway management system architecture is modelled as a network of communicating finite state machines. Architecture-level behaviours are validated using the Labelled Transition System Analyzer (LTSA). We exercise the methodology by working step by step through the synthesis and validation of a high-level behaviour model for a vessel passing through a waterway network (i.e., canal)

APTs way: evading Your EBNIDS

APTs and government-supported attackers use a broad arsenal of techniques to avoid having their exploits detected by IDSes. Signature Based IDSes are not efficient against nation-state-sponsored attackers which use custom shellcode encoders in an exploit. Emulation Based NIDSes (EBNIDS) have been proposed as a solution to mitigate such attacks. EBNISes detect a suspicious network stream (pre-processing) and after converting them to emulate-able byte sequences run it in an instrumented environment (Emulation), finally matching the behavior with certain heuristics (Heuristics Detection). In this talk, we will present novel ways that an APT might use to circumvente the Pre-Processing, Emulation and Heuristic Detection steps of EBNIDSes by employing a wide range of evasion techniques