1,107 research outputs found
Algorithmic Aspects of Cyclic Combinational Circuit Synthesis
Digital circuits are called combinational if they are memoryless: if they have outputs that depend only on the current values of the inputs. Combinational circuits are generally thought of as acyclic (i.e., feed-forward) structures. And yet, cyclic circuits can be combinational. Cycles sometimes occur in designs synthesized from high-level descriptions, as well as in bus-based designs [16]. Feedback in such cases is carefully contrived, typically occurring when functional units are connected in a cyclic topology. Although the premise of cycles in combinational circuits has been accepted, and analysis techniques have been proposed [7], no one has attempted the synthesis of circuits with feedback at the logic level.
We have argued the case for a paradigm shift in combinational circuit design [10]. We should no longer think of combinational logic as acyclic in theory or in practice, since most combinational circuits are best designed with cycles. We have proposed a general methodology for the synthesis of multilevel networks with cyclic topologies and incorporated it in a general logic synthesis environment. In trials, benchmark circuits were optimized significantly, with improvements of up to 30%I n the area. In this paper, we discuss algorithmic aspects of cyclic circuit design. We formulate a symbolic framework for analysis based on a divide-and-conquer strategy. Unlike previous approaches, our method does not require ternary-valued simulation. Our analysis for combinationality is tightly coupled with the synthesis phase, in which we assemble a combinational network from smaller combinational components. We discuss the underpinnings of the heuristic search methods and present examples as well as synthesis results for benchmark circuits.
In this paper, we discuss algorithmic aspects of cyclic circuit design. We formulate a symbolic framework for analysis based on a divide-and-conquer strategy. Unlike previous approaches, our method does not require ternary-valued simulation. Our analysis for combinationality is tightly coupled with the synthesis phase, in which we assemble a combinational network from smaller combinational components. We discuss the underpinnings of the heuristic search methods and present examples as well as synthesis results for benchmark circuits
COPAS: A New Algorithm for the Partial Input Encoding Problem
Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols should be chosen to optimize the final implementation. Conventionally, this input encoding (IE) problem has been solved in a two-step process. First step generates constraints on the relationship between codes for different symbols, called group constraints. In a following step, symbols are encoded such that constraints are satisfied. This paper addresses the partial input encoding problem (PIE), a variation of the IE problem which generates codes of minimum length. The role of group constraints within the framework of the PIE problem has been questioned. This paper describes an algorithm that unlike conventional approaches, which try to maximize the number of satisfied constraints, targets the economical implementation of each input constraint. The proposed approach is based on a powerful heuristic that produces high quality results in shorter time compared to previous algorithm
Efficient state reduction methods for PLA-based sequential circuits
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems
Synthesis for Logical Initializability of Synchronous Finite State Machines
A new method is introduced for the synthesis for logical initializability of synchronous state machines. The goal is to synthesize a gate-level implementation that is initializable when simulated by a 3-valued (0,1,X) simulator. The method builds on an existing approach of Cheng and Agrawal, which uses constrained state assignment to translate functional initializability into logical initializability. Here, a different state assignment method is proposed which, unlike the method of Cheng and Agrawal, is guaranteed safe and yet is not as conservative. Furthermore, it is demonstrated that certain new constraints on combinational logic synthesis are both necessary and sufficient to insure that the resulting gate-level circuit is 3-valued simulatable. Interestingly, these constraints are similar to those used for hazard-free synthesis of asynchronous combinational circuits. Using the above constraints, we present a complete synthesis for initializability method, targeted to both two-level and multi-level circuits
Efficient Decompression of Binary Encoded Balanced Ternary Sequences
International audienceA balanced ternary digit, known as a trit, takes its values in {-1, 0, 1}. It can be encoded in binary as {11, 00, 01} for direct use in digital circuits. In this correspondence, we study the decompression of a sequence of bits into a sequence of binary encoded balanced ternary digits. We first show that it is useless in practice to compress sequences of more than 5 ternary values. We then provide two mappings, one to map 5 bits to 3 trits and one to map 8 bits to 5 trits. Both mappings were obtained by human analysis and lead to Boolean implementations that compare quite favorably with others obtained by tweaking assignment or encoding optimization tools. However, mappings that lead to better implementations may be feasible
Low-power FSMs in FPGA: Encoding alternatives
The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-45716-X_36Proceedings of 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57% can be achieved selecting the appropriate encoding. An areapower correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.Ministry of Science of Spain, under Contract TIC2001-2688-C03-03, has supported
this work. Additional funds have been obtained from Projects 658001 and 658004 of
the Fundación General de la Universidad Autónoma de Madrid
Backwards is the way forward: feedback in the cortical hierarchy predicts the expected future
Clark offers a powerful description of the brain as a prediction machine, which offers progress on two distinct levels. First, on an abstract conceptual level, it provides a unifying framework for perception, action, and cognition (including subdivisions such as attention, expectation, and imagination). Second, hierarchical prediction offers progress on a concrete descriptive level for testing and constraining conceptual elements and mechanisms of predictive coding models (estimation of predictions, prediction errors, and internal models)
An FSM Re-Engineering Approach to Sequential Circuit Synthesis by State Splitting
We propose Finite State Machine (FSM) re-engineering, a
performance enhancement framework for FSM synthesis and
optimization. It starts with the traditional FSM synthesis procedure,
then proceeds to re-construct a functionally equivalent
but topologically different FSM based on the optimization
objective, and concludes with another round of FSM synthesis
on the re-constructed FSM. This approach explores a larger
solution space that consists of a set of FSMs functionally
equivalent to the original one, making it possible to obtain
better solutions than in the original FSM. Guided by the result
from the #2;rst round of synthesis, the solution space exploration
process can be rapid and cost-ef#2;cient.
We apply this framework to FSM state encoding for power
minimization and area minimization. The FSM is #2;rst minimized
and encoded using existing state encoding algorithms.
Then we develop both a heuristic algorithm and a genetic
algorithm to re-construct the FSM. Finally, the FSM is reencoded
by the same encoding algorithms. To demonstrate
the effectiveness of this framework, we conduct experiments
on MCNC91 sequential circuit benchmarks. The circuits are
read in and synthesized in SIS environment. After FSM
re-engineering are performed, we measure the power, area
and delay in the newly synthesized circuits. In the powerdriven
synthesis, we observe an average 5.5% of total power
reduction with 1.3% area increase and 1.3% delay increase.
This results are in general better than other low power state
encoding techniques on comparable cases. In the area-driven
synthesis, we observe an average 2.7% area reduction, 1.8%
delay reduction, and 0.4% power increase. Finally, we use
integer linear programming to obtain the optimal low power
state encoding for benchmarks of small size. We #2;nd that the
optimal solutions in the re- engineered FSMs are 1% to 8%
better than the optimal solutions in the original FSMs in terms
of power minimization
- …