An error-controlled methodology for approximate hierarchical symbolic analysis

Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results.European Commission ESPRIT 21812Comisión Interministerial de Ciencia y Tecnología TIC97-058

Pathological element-based active device models and their application to symbolic analysis

This paper proposes new pathological element-based active device models which can be used in analysis tasks of linear(ized) analog circuits. Nullators and norators along with the voltage mirror-current mirror (VM-CM) pair (collectively known as pathological elements) are used to model the behavior of active devices in voltage-, current-, and mixed-mode, also considering parasitic elements. Since analog circuits are transformed to nullor-based equivalent circuits or VM-CM pairs or as a combination of both, standard nodal analysis can be used to formulate the admittance matrix. We present a formulation method in order to build the nodal admittance (NA) matrix of nullor-equivalent circuits, where the order of the matrix is given by the number of nodes minus the number of nullors. Since pathological elements are used to model the behavior of active devices, we introduce a more efficient formulation method in order to compute small-signal characteristics of pathological element-based equivalent circuits, where the order of the NA matrix is given by the number of nodes minus the number of pathological elements. Examples are discussed in order to illustrate the potential of the proposed pathological element-based active device models and the new formulation method in performing symbolic analysis of analog circuits. The improved formulation method is compared with traditional formulation methods, showing that the NA matrix is more compact and the generation of nonzero coefficients is reduced. As a consequence, the proposed formulation method is the most efficient one reported so far, since the CPU time and memory consumption is reduced when recursive determinant-expansion techniques are used to solve the NA matrix.Promep-Mexico UATLX-PTC-088Junta de Andalucía TIC-2532Ministerio de Educación y Ciencia TEC2007-67247, TEC2010-14825UC-MEXUS-CONACyT CN-09-31

Symbolic analysis of analog circuits containing voltage mirrors

7 páginas, 7 figuras, 2 tablas, 4 imágenes.-- Open Access: This article is distributed under the terms of the Creative Commons Attribution Noncommercial License.The pathological elements voltage mirror (VM) and current mirror (CM) have shown advantages in analog behavioral modeling and circuit synthesis, where many nullor-mirror equivalences have been explored to design and to transform voltage-mode circuits to current-mode ones and viceversa. However, both the VM and CM have not equivalents to perform automatic symbolic circuit analysis. In this manner, we introduce nullor-equivalents for these pathological elements allowing to include parasitics and to perform only symbolic nodal analysis. The nullor-equivalent of the CM is extended to provide multiple-outpus (MO-CM). Finally, two active filters containing VMs, CMs and MO-CMs are analysed to show the usefulness of the models.This work is supported by: UC-MEXUS and CONACyT under grants CN-09-310 and 48396-Y; by Promep-Mexico under grant UATLX-PTC-088; by Consejeria de Innovacion, Ciencia y Empresa, Junta de Andalucia-Spain TIC-2532; and by the JAE-Doc program of CSIC co-funded by FSE, Spain.Peer reviewe

Behavioral Modeling of Mixed-Mode Integrated Circuits

Open Access.-- et al.This work is partially supported by CONACyT through the grant for the sabbatical stay of the first author at University of California at Riverside, during 2009-2010. The authors acknowledge the support from UC-MEXUS-CONACYT collaboration grant CN-09-310; by Promep México under the project UATLX-PTC-088, and by Consejeria de Innovacion Ciencia y Empresa, Junta de Andalucia, Spain, under the project number TIC-2532. The third author thanks the support of the JAE-Doc program of CSIC, co-funded by FSE.Peer Reviewe

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Implementation of a Symbolic Circuit Simulator for Topological Network Analysis

Abstract- Many topological approaches to symbolic network analysis have been proposed in the literature, but none are implemented ultimately as a simulator for large network analysis due to their complexity and exponentially increasing number of terms. A novel methodology adopted in this paper uses a graph reduction approach based on a set of graph reduction rules developed recently. Furthermore, a Binary Decision Diagram is used in the implementation of a symbolic simulator that is capable of analyzing large analog circuit blocks. Implementation details and experimental results are reported. Keywords-admissible term, BDD, graph reduction, symbolic analysis I