Parallel Connected VSI Inverter using Multi-carrier based Sinusoidal PWM Technique

This paper explains the simulation and modelling of Parallel operation of VSI inverter using multi-carrier based PWM technique. By this proposed method three level inverter output voltages generated instead of using multilevel inverter or two level dual VSI inverter. This system employs single dc voltage source, which gives supply to both VSI inverter by using parallel connection. The multi-carrier based pulse width modulation technique affianced to control the inverter power switches. The proposed system offers improved output voltage, better current control and reduced harmonic distortion. The simulation results of this proposed system was verified using matlab/simulink

An Advanced Three-Level Active Neutral-Point-Clamped Converter With Improved Fault-Tolerant Capabilities

A resilient fault-tolerant silicon carbide (SiC) three-level power converter topology is introduced based on the traditional active neutral-point-clamped converter. This novel converter topology incorporates a redundant leg to provide fault tolerance during switch open-circuit faults and short-circuit faults. Additionally, the topology is capable of maintaining full output voltage and maximum modulation index in the presence of switch open and short-circuit faults. Moreover, the redundant leg can be employed to share load current with other phase legs to balance thermal stress among semiconductor switches during normal operation. A 25-kW prototype of the novel topology was designed and constructed utilizing 1.2-kV SiC metal-oxide-semiconductor field-effect transistors. Experimental results confirm the anticipated theoretical capabilities of this new three-level converter topology

Dimensionnement des éléments passifs d'un convertisseur cascadé en vue de l'intégration d'organes de stockage au réseau

International audienceNous présentons dans ce papier une méthode de dimensionnement des éléments passifs d'un convertisseur multi-niveaux de topologie ponts complets cascadés. Ce convertisseur est assemblé en étoile et intègre des batteries de stockage chimique. La topologie présente une bonne tolérance aux défauts et permet une montée en tension plus facile. Les éléments passifs du convertisseur, tels que les inductances de ligne et les condensateurs de bus continu sont quantifiés de manière générique en fonction du nombre de modules.Les modèles de dimensionnement, couplés à une fonction objectif, permettent de mettre en place un algorithme de dimensionnement optimal du convertisseur multi-niveau, permettant de choisir le nombre de niveaux en optimisant un rapport coût/volume/performance moins restrictif comparé à une approche classique.</p

A fault-tolerant photovoltaic integrated shunt active power filter with a 27-level inverter

This paper introduces a fault-tolerant shunt active power filter (SAPF). The novility in of this work is that it poposes a solutions to increase the reliability of shunt active power filter to maintain its operation under a single-phase open-circuit fault in the SAPF. This will increase the reliability of the whole power system. The SAPF is composed of a 4-leg 27-level inverter based on asymmetric cascaded H-bridge topology. If an open-circuit fault is introduced to the operation of the SAPF, a special control technique will be implemented and the redundant leg of the SAPF will be activated. The fault-tolerant SAPF can do many tasks under healthy operating conditions and post and open circuit fault depending on the state of charge (SOC) of the batteries. It can mitigate harmonics in the power system, improve power factor in the system by injecting reactive power, and inject real power to the system. The proposed SAPF is tested and simulated in MATLAB/Simulink and the results have shown a significant improvement in total harmonics distortion (THD) of the source current from 13.9% to 3.9% under the normal operating condition and from 42% to 8.4% post and open circuit fault

A novel single source three phase seven-level inverter topology for grid-tied photovoltaic application

This paper presents a novel single-source three-phase multilevel inverter structure with voltage boosting capability, which is suitable for medium-voltage photovoltaic (PV) applications. The proposed structure consists of switched-capacitors (SCs) based multilevel dc-link stages that boost-up the input DC-source voltage significantly. It reduces the dc-link voltage requirements by 75% compared to the traditional neutral point clamped (NPC), flying capacitors (FCs), active NPC (ANPC), hybrid and hybrid clamped ANPC and cascaded h-bridge (CHB) topologies, and 50% compared to advanced ANPC topologies. The proposed structure also reduces the number of required switches and capacitors as well as their voltages stresses compared to these state-of-the-art topologies. A robust control scheme based on finite control set model predictive control (FCS-MPC) is derived to control the converter. The capacitor voltage balancing is inherent of the proposed topology, and thus, eliminates the need for additional voltage balancing circuit and reduces the control complexity

Distributed control of a fault tolerant modular multilevel inverter for direct-drive wind turbine grid interfacing

Modular generator and converter topologies are being pursued for large offshore wind turbines to achieve fault tolerance and high reliability. A centralized controller presents a single critical point of failure which has prevented a truly modular and fault tolerant system from being obtained. This study analyses the inverter circuit control requirements during normal operation and grid fault ride-through, and proposes a distributed controller design to allow inverter modules to operate independently of each other. All the modules independently estimate the grid voltage magnitude and position, and the modules are synchronised together over a CAN bus. The CAN bus is also used to interleave the PWM switching of the modules and synchronise the ADC sampling. The controller structure and algorithms are tested by laboratory experiments with respect to normal operation, initial synchronization to the grid, module fault tolerance and grid fault ride-through

Design and implementation of a novel three-phase cascaded half-bridge inverter

In this study, a new circuit topology of a three-phase half-bridge multilevel inverter (MLI) is proposed. The proposed MLI that consists of a cascaded half-bridge structure along with a modified full-bridge structure requires less number of dc-power supplies and power semiconductor devices, e.g. insulated gate bipolar transistors and diodes when compared with the existing MLI topologies, which significantly reduces the size and cost of the inverter. Two different structures: isolated and non-isolated dc-power supply-based three-phase half-bridge MLIs are investigated. A number of generalised methods are proposed to determine the magnitude of the input dc-power supplies that has a great impact on the number of levels of the output voltage waveform. To verify the feasibility of the proposed MLI topology, a scaled down laboratory prototype three-phase half-bridge MLI is developed and the experimental results are analysed and compared with the simulation results. Experimental and simulation results reveal the feasibility and excellent features of the proposed inverter system

Fast Reliability Assessment of Neutral-Point-Clamped Topologies through Markov Models

This article presents detailed Markov models for the reliability assessment of multilevel neutral-point-clamped (NPC) converter leg topologies, incorporating their inherent fault-tolerance under open-circuit switch faults. The Markov models are generated and discussed in detail for the three-level and four-level active NPC (ANPC) cases, while the presented methodology can be applied to easily generate the models for a higher number of levels and other topology variants. In addition, this article also proposes an extremely fast calculation method to obtain the precise value of the system's mean time to failure from any given formulated system Markov model. This method is then applied to quantitatively compare the reliability of two-level, three-level, and four-level ANPC legs under switch open-circuit-guaranteed faults and varying degrees of device paralleling. The comparison reveals that multilevel ANPC leg topologies inherently present a potential for higher reliability than the conventional two-level leg, questioning the suitability of the traditional search for topologies with the minimum number of devices in order to improve reliability. Experimental results are presented to validate the fault-tolerance assumptions upon which the presented reliability models for the three-level and four-level ANPC legs are based. This article is accompanied by supplementary MATLAB scripts.Peer Reviewed© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work