Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (s) are the highest when compared to other reported FCOTAs in the literature

Super class AB RFC OTA with adaptive local common-mode feedback

A super class AB recycling folded cascode operational transconductance amplifier is presented. It employs local common-mode feedback using two matched tuneable active resistors, allowing to adapt the amplifier to different process variations and loads. Measurement results from a test chip prototype fabricated in a 0.5 μm CMOS process validate the proposal

Energy-efficient amplifiers based on quasi-floating gate techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage ultra low power amplifiers can be designed preserving at the same time excellent small-signal and large-signal performance.This research was funded by AEI/FEDER, grant number PID2019-107258RB-C32

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.Agencia Estatal de Investigación PID2019-107258RB-C32Unión Europea PID2019-107258RB-C3

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results