Ultra Low Power Circuits for Internet of Things and Deep Learning Accelerator Design with In-Memory Computing

Collecting data from environment and converting gathered data into information is the key idea of Internet of Things (IoT). Miniaturized sensing devices enable the idea for many applications including health monitoring, industrial sensing, and so on. Sensing devices typically have small form factor and thus, low battery capacity, but at the same time, require long life time for continuous monitoring and least frequent battery replacement. This thesis introduces three analog circuit design techniques featuring ultra-low power consumption for such requirements: (1) An ultra-low power resistor-less current reference circuit, (2) A 110nW resistive frequency locked on-chip oscillator as a timing reference, (3) A resonant current-mode wireless power receiver and battery charger for implantable systems. Raw data can be efficiently transformed into useful information using deep learning. However deep learning requires tremendous amount of computation by its nature, and thus, an energy efficient deep learning hardware is highly demanded to fully utilize this algorithm in various applications. This thesis also presents a pulse-width based computation concept which utilizes in-memory computing of SRAM.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/144173/1/myungjun_1.pd

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

Biomedical Amplifiers Design Based on Pseudo-resistors: A Review

The demand for efficient, robust, and cost-effective Brain-Machine Interface (BMI) systems continues to increase in the last decade. One of the fundamental design blocks in such systems is the signal amplification and filtering. Generally, biomedical signals are characterized by low amplitude and low frequency in a noisy environment. Therefore they need to be amplified and filtered before passing the signal to the next processing stage. In this review paper, a comprehensive survey is conducted in existing literature of two-stage biomedical amplifiers, focusing on the impact of the pseudo-resistor non-linearity on the system’s performance. First, the common categories of pseudo-resistors are presented and discussed. Then, different amplifier designs, targeted for biomedical applications, are identified and studied considering the influence of the pseudo-resistors on the performance. A special focus was given to the impact of the Process, Voltage, and Temperature variations where experiments are conducted to test the performance under different variation tests. Different two-stage biomedical amplifiers, used in bio-detection systems, with programmable gain and bandwidth features based on pseudo-resistors are implemented. The designs are realized and simulated using LTspice utilizing 90nm process technology, BSIM4, version 4.3, level 54

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Nano-Watt Modular Integrated Circuits for Wireless Neural Interface.

In this work, a nano-watt modular neural interface circuit is proposed for ECoG neuroprosthetics. The main purposes of this work are threefold: (1) optimizing the power-performance of the neural interface circuits based on ECoG signal characteristics, (2) equipping a stimulation capability, and (3) providing a modular system solution to expand functionality. To achieve these aims, the proposed system introduces the following contributions/innovations: (1) power-noise optimization based on the ECoG signal driven analysis, (2) extreme low-power analog front-ends, (3) Manchester clock-edge modulation clock data recovery, (4) power-efficient data compression, (5) integrated stimulator with fully programmable waveform, (6) wireless signal transmission through skin, and (7) modular expandable design. Towards these challenges and contributions, three different ECoG neural interface systems, ENI-1, ENI-16, and ENI-32, have been designed, fabricated, and tested. The first ENI system(ENI-1) is a one-channel analog front-end and fabricated in a 0.25µm CMOS process with chopper stabilized pseudo open-loop preamplifier and area-efficient SAR ADC. The measured channel power, noise and area are 1.68µW at 2.5V power-supply, 1.69µVrms (NEF=2.43), and 0.0694mm^2, respectively. The fabricated IC is packaged with customized miniaturized package. In-vivo human EEG is successfully measured with the fabricated ENI-1-IC. To demonstrate a system expandability and wireless link, ENI-16 IC is fabricated in 0.25µm CMOS process and has sixteen channels with a push-pull preamplifier, asynchronous SAR ADC, and intra-skin communication(ISCOM) which is a new way of transmitting the signal through skin. The measured channel power, noise and area are 780nW, 4.26µVrms (NEF=5.2), and 2.88mm^2, respectively. With the fabricated ENI-16-IC, in-vivo epidural ECoG from monkey is successfully measured. As a closed-loop system, ENI-32 focuses on optimizing the power performance based on a bio-signal property and integrating stimulator. ENI-32 is fabricated in 0.18µm CMOS process and has thirty-two recording channels and four stimulation channels with a cyclic preamplifier, data compression, asymmetric wireless transceiver (Tx/Rx). The measured channel power, noise and area are 140nW (680nW including ISCOM), 3.26µVrms (NEF=1.6), and 5.76mm^2, respectively. The ENI-32 achieves an order of magnitude power reduction while maintaining the system performance. The proposed nano-watt ENI-32 can be the first practical wireless closed-loop solution with a practically miniaturized implantable device.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98064/1/schang_1.pd

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

Wearable, low-power CMOS ISFETs and compensation circuits for on-body sweat analysis

Complementary metal-oxide-semiconductor (CMOS) technology has been a key driver behind the trend of reduced power consumption and increased integration of electronics in consumer devices and sensors. In the late 1990s, the integration of ion-sensitive field-effect transistors (ISFETs) into unmodified CMOS helped to create advancements in lab-on-chip technology through highly parallelised and low-cost designs. Using CMOS techniques to reduce power and size in chemical sensing applications has already aided the realisation of portable, battery-powered analysis platforms, however the possibility of integrating these sensors into wearable devices has until recently remained unexplored. This thesis investigates the use of CMOS ISFETs as wearable electrochemical sensors, specifically for on-body sweat analysis. The investigation begins by evaluating the ISFET sensor for wearable applications, identifying the key advantages and challenges that arise in this pursuit. A key requirement for wearable devices is a low power consumption, to enable a suitable operational life and small form factor. From this perspective, ISFETs are investigated for low power operation, to determine the limitations when trying to push down the consumption of individual sensors. Batteryless ISFET operation is explored through the design and implementation of a 0.35 \si{\micro\metre} CMOS ISFET sensing array, operating in weak-inversion and consuming 6 \si{\micro\watt}. Using this application-specific integrated circuit (ASIC), the first ISFET array powered by body heat is demonstrated and the feasibility of using near-field communication (NFC) for wireless powering and data transfer is shown. The thesis also presents circuits and systems for combatting three key non-ideal effects experienced by CMOS ISFETs, namely temperature variation, threshold voltage offset and drift. An improvement in temperature sensitivity by a factor of three compared to an uncompensated design is shown through measured results, while adding less than 70 \si{\nano\watt} to the design. A method of automatically biasing the sensors is presented and an approach to using spatial separation of sensors in arrays in applications with flowing fluids is proposed for distinguishing between signal and sensor drift. A wearable device using the ISFET-based system is designed and tested with both artificial and natural sweat, identifying the remaining challenges that exist with both the sensors themselves and accompanying components such as microfluidics and reference electrode. A new ASIC is designed based on the discoveries of this work and aimed at detecting multiple analytes on a single chip. %Removed In the latter half of the thesis, Finally, the future directions of wearable electrochemical sensors is discussed with a look towards embedded machine learning to aid the interpretation of complex fluid with time-domain sensor arrays. The contributions of this thesis aim to form a foundation for the use of ISFETs in wearable devices to enable non-invasive physiological monitoring.Open Acces