709 research outputs found
AnalogâtoâDigital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing
This chapter explores different analog-to-digital conversion techniques that are suitable to be implemented in cognitive radio receivers. This chapter details the fundamentals, advantages, and drawbacks of three promising techniques: subsampling, interleaving, and compressive sensing. Due to their major maturity, subsampling- and interleaving-based systems are described in further detail, whereas compressive sensing-based systems are described as a complement of the previous techniques for underutilized spectrum applications. The feasibility of these techniques as part of software-defined radio, multistandard, and spectrum sensing receivers is demonstrated by proposing different architectures with reduced complexity at circuit level, depending on the application requirements. Additionally, the chapter proposes different solutions to integrate the advantages of these techniques in a unique analog-to-digital conversion process
Compressive Sensing for Spread Spectrum Receivers
With the advent of ubiquitous computing there are two design parameters of
wireless communication devices that become very important power: efficiency and
production cost. Compressive sensing enables the receiver in such devices to
sample below the Shannon-Nyquist sampling rate, which may lead to a decrease in
the two design parameters. This paper investigates the use of Compressive
Sensing (CS) in a general Code Division Multiple Access (CDMA) receiver. We
show that when using spread spectrum codes in the signal domain, the CS
measurement matrix may be simplified. This measurement scheme, named
Compressive Spread Spectrum (CSS), allows for a simple, effective receiver
design. Furthermore, we numerically evaluate the proposed receiver in terms of
bit error rate under different signal to noise ratio conditions and compare it
with other receiver structures. These numerical experiments show that though
the bit error rate performance is degraded by the subsampling in the CS-enabled
receivers, this may be remedied by including quantization in the receiver
model. We also study the computational complexity of the proposed receiver
design under different sparsity and measurement ratios. Our work shows that it
is possible to subsample a CDMA signal using CSS and that in one example the
CSS receiver outperforms the classical receiver.Comment: 11 pages, 11 figures, 1 table, accepted for publication in IEEE
Transactions on Wireless Communication
Cognitive Sub-Nyquist Hardware Prototype of a Collocated MIMO Radar
We present the design and hardware implementation of a radar prototype that
demonstrates the principle of a sub-Nyquist collocated multiple-input
multiple-output (MIMO) radar. The setup allows sampling in both spatial and
spectral domains at rates much lower than dictated by the Nyquist sampling
theorem. Our prototype realizes an X-band MIMO radar that can be configured to
have a maximum of 8 transmit and 10 receive antenna elements. We use frequency
division multiplexing (FDM) to achieve the orthogonality of MIMO waveforms and
apply the Xampling framework for signal recovery. The prototype also implements
a cognitive transmission scheme where each transmit waveform is restricted to
those pre-determined subbands of the full signal bandwidth that the receiver
samples and processes. Real-time experiments show reasonable recovery
performance while operating as a 4x5 thinned random array wherein the combined
spatial and spectral sampling factor reduction is 87.5% of that of a filled
8x10 array.Comment: 5 pages, Compressed Sensing Theory and its Applications to Radar,
Sonar and Remote Sensing (CoSeRa) 201
Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements
The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver
Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers
In the field of radio receivers, down-conversion methods usually rely on one (or more)
explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not
only contribute to the overall power consumption but also have an impact on area and can
compromise the receiverâs performance in terms of noise and linearity. On the other hand,
most ADCs require some sort of reference signal in order to properly digitize an analog
input signal. The implementation of this reference signal usually relies on bandgap
circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this
conventional approach, the work developed in this thesis aims to explore the viability
behind the usage of a variable reference signal. Moreover, it demonstrates that not only
can an input signal be properly digitized, but also shifted up and down in frequency,
effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver
chains can perform double-duty as both a quantizer and a mixing stage. The lesser known
charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs,
is used for a practical implementation, due to its feature of âpre-chargingâ the reference
signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in
a 0.13 ÎŒm CMOS technology validate the proposed technique
Data Acquisition Applications
Data acquisition systems have numerous applications. This book has a total of 13 chapters and is divided into three sections: Industrial applications, Medical applications and Scientific experiments. The chapters are written by experts from around the world, while the targeted audience for this book includes professionals who are designers or researchers in the field of data acquisition systems. Faculty members and graduate students could also benefit from the book
Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio
A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation
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