Implementation of a 200 MSps 12-bit SAR ADC

Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. In this thesis a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was designed for a 28 nm CMOS technology. The proposed design uses an efficient SAR algorithm (merged capacitor switching procedure) to reduce power consumption due to capacitor charging by 88 % compared to a conventional design, as well as reducing the total capacitor area by half. Sampling switches were bootstrapped for increased linearity compared to simple transmission gates. Another feature of the low power design is a fully-dynamic comparator which does not require a preamplifier. Pre-layout simulations of the SAR ADC with 800 MHz input frequency shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR of 75.3 dB. The total power consumption is 1.77 mW with an estimated value of 500 W for the unimplemented digital logic. Calculation of the Schreier figure-of-merit was done with an input signal at the Nyquist frequency. The simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW respectively, corresponding to a figure-of merit of 176.6 dB.Från analogt till digitalt - snabba och strömsnåla omvandlare Dagens digitala samhälle ställer höga krav på prestanda och effektivitet. I samarbete med Ericsson i Lund har en krets för signalomvandling utvecklats. Genom smart design uppnås hög hastighet och låg strömförbrukning som ligger i forskningens framkant. Från analogt till digitalt Ett viktigt byggblock för telekommunikation och videoapplikationer är så kallade A/D-omvandlare, som översätter mellan analoga signaler (till exempel ljud) och digitala signaler bestående av ettor och nollor. En väldigt effektiv metod för A/D-omvandling bygger på så kallad successiv approximation. Metoden innebär att signalen som ska omvandlas jämförs med en referensnivå, som stegvis justeras för att närma sig signalens värde. Till slut har man en tillräckligt god uppskattning av värdet som ska mätas. Just en sådan omvandlare har utvecklats med höga krav på hastighet och energiförbrukning. Detta gjordes genom datorsimuleringar av modeller som beskriver kretsen. Referensnivån skapas ofta genom att styra ett nätverk som lagrar elektrisk laddning. Omvandlingens noggrannhet, eller upplösning, beror på hur många nivåer som finns tillgängliga det vill säga hur nära signalens värde man kan komma. I den designade kretsen finns hela 4096 nivåer! Det finns många källor till osäkerhet i systemet, bland annat hur exakta referensnivåerna är och hur bra jämförelsen med insignalen kan göras. Eftersom dessa eventuellt kan leda till en försämring av omvandlingens noggrannhet måste alla delar i kretsen utformas med detta i åtanke. Höga hastigheter Eftersom det krävs många steg för referensnivån att närma sig signalens värde är den maximala omvandlingshastigheten ofta begränsad. Med teknikens utveckling öppnas nya möjligheter i takt med att mikrochippens enskilda komponenter blir snabbare. Modern forskning visar att omvandlare baserade på successiv approximation kan uppnå hastigheter på flera miljoner mätvärden varje sekund, vilket även den utvecklade kretsen klarar av. Effektiv design Nya metoder för successiv approximation möjliggör stora besparingar när det gäller effektförbrukning, till exempel genom att effektivisera upp- och urladdningen av nätverket. Genom små ändringar kunde nätverkets energiförbrukning minskas med över 90 % samtidigt som dess area halverades. Eftersom produktionskostnaden för integrerade kretsar är hög medför varje minskning av kretsens area att kostnaden sjunker

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

Study and application of direct RF power injection methodology and mitigation of electromagnetic interference in ADCs

There are many publications available in literature regarding the DPI (Direct Power Injection) technique for electronic systems, but few works specifically addressed for mixed-signal converters, which are components existent in almost all electronic devices. IEC 62132-4(International Electrotechnical Commission, 2006) and 62132-1(International Electrotechnical Commission, 2006) standards describe a method for measuring immunity of integrated circuits (IC) in the presence of conducted RF disturbances. This method ensures a high degree of repeatability and correlation of immunity measurements. Knowledge of the electromagnetic immunity of an IC allows the designer to decide if the system will need external protection, and how much effort should be directed to this solution. In this context, the purpose of this work is the study and application of the DPI methodology for injection of EMI in a mixed-signal programmable device, evaluating mitigation possibilities, with special focus on the analog-to-digital converters (ADCs). The main objective is to evaluate the impact of electromagnetic interference (EMI) on different converters (two Successive Approximation Register ADCs, operating with distinct sampling rate and a Sigma-Delta ADC) of the Cypress Semiconductor Programmable SoC (System-on-Chip), PSoC 5LP. Additionally a previously proposed fault tolerance methodology, based on triplication with hardware and time diversity is tested. Results show distinct behaviors of each converter to conducted EMI. Finally, the tested tolerance technique showed to be suitable to reduce error rate of such data acquisition system operating under EMI disturbance.Existem muitas publicações disponíveis na literatura sobre a técnica de DPI (Direct Power Injection ou injeção direta de energia) para sistemas eletrônicos, mas poucos trabalhos direcionados para conversores de sinais mistos, que são componentes existentes em quase todos os dispositivos eletrônicos. As normas IEC 62132-4 (IEC, 2006) e 62132-1 (IEC, 2006) descrevem um método para medir a imunidade de circuitos integrados (CI) na presença de distúrbios de RF conduzidos. Este método garante um alto grau de repetibilidade e correlação das medições da imunidade. O conhecimento da imunidade eletromagnética de um CI permite que o projetista decida se o sistema precisará de proteção externa e quanto esforço deve ser direcionado para esta solução. Nesse contexto, o objetivo deste trabalho é o estudo e aplicação da metodologia DPI para injeção de interferência eletromagnética em um dispositivo programável de sinal misto, avaliando as possibilidades de mitigação, com foco especial em conversores analógico-digitais (ADCs). O principal objetivo é avaliar o impacto da interferência eletromagnética em diferentes conversores (dois ADCs baseados em aproximação sucessiva, operando com taxa de amostragem distintas e um ADC do tipo Sigma-Delta) do SoC(System-on-Chip) programável da Cypress Semiconductor, PSoC 5LP. Além disso, é testada uma metodologia de tolerância a falhas proposta anteriormente, baseada em triplicação com diversidade de hardware e temporal. Os resultados mostram comportamentos distintos de cada conversor para a interferência eletromagnética conduzida. Finalmente, a técnica de tolerância testada mostrou-se adequada para reduzir a taxa de erros desse sistema de aquisição de dados operando sob perturbação eletromagnética

Energy and area efficient techniques for data converters

Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art analog to digital converters. Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the motivation for this research. This research focuses on achieving this goal by enabling circuit techniques, architecture techniques and calibration methods. The following techniques are proposed for enabling power, area and energy efficient analog to digital converter techniques. 1. A capacitor switching scheme for successive approximation ADC is introduced to enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a conventional SAR ADCs. 2. Asynchronous correlated level shifting technique for improving current source linearity and power supply rejection ratio of zero crossing based circuits is proposed. This technique enables asynchronous ADC architectures for energy efficient system. 3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques. Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are introduced as parallel gain enhancement techniques for switched capacitor circuits. A prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR, 87 dB THD at 20 MS/s. Built in 1P4M 0.18 μm technology and operating at 1.3 V supply, the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB THD at 30 MS /s in a 0.18 μm process. The ADC consumes 6.6 mW from a 1.3 V supply and achieves a figure of merit of 40 fJ/C-S. 4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace the function of flash ADC and the DAC references in a pipeline ADC. The simulated/ extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming approximately 8-9 mA from 1 V supply. 5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed. This multi-path ADC technique squares the bit-error rate of the ADC without consuming additional analog power. The area increase is negligible compared to the conventional modular redundancy techniques. This technique can be applied to digitally detect and correct single event transients for ADCs. A three-path ADC can restore the ADC performance independent of the input frequency and number of errors in a single path. 6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity

Testing a fault tolerant mixed-signal design under TID and heavy ions

This work presents results of three distinctradiation tests performed upon a fault tolerant data acqui-sition system comprising a design diversity redundancytechnique. The first and second experiments are Total Ion-izing Dose (TID) essays, comprising gamma and X-rayirradiations. The last experiment considers single eventeffects, in which two heavy ion irradiation campaignsare carried out. The case study system comprises threeanalog-to-digital converters and two software-based vot-ers, besides additional software and hardware resourcesused for controlling, monitoring and memory manage-ment. The applied Diversity Triple Modular Redundancy(DTMR) technique, comprises different levels of diversity(temporal and architectural). The circuit was designed ina programmable System-on-Chip (PSoC), fabricated in a130nm CMOS technology process. Results show that thetechnique may increase the lifetime of the system underTID if comparing with a non-redundant implementation.Considering the heavy ions experiments the system wasproved effective to tolerate 100% of the observed errorsoriginated in the converters, while errors in the process-ing unit present a higher criticality. Critical errors occur-ring in one of the voters were also observed. A secondheavy ion campaign was then carried out to investigatethe voters reliability, comparing the the dynamic cross sec-tion of three different software-based voter schemes im-plemented in the considered PSoC

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Ultra-low Power Circuits and Architectures for Neuromorphic Computing Accelerators with Emerging TFETs and ReRAMs

Neuromorphic computing using post-CMOS technologies is gaining increasing popularity due to its promising potential to resolve the power constraints in Von-Neumann machine and its similarity to the operation of the real human brain. To design the ultra-low voltage and ultra-low power analog-to-digital converters (ADCs) for the neuromorphic computing systems, we explore advantages of tunnel field effect transistor (TFET) analog-to-digital converters (ADCs) on energy efficiency and temperature stability. A fully-differential SAR ADC is designed using 20 nm TFET technology with doubled input swing and controlled comparator input common-mode voltage. To further increase the resolution of the ADC, we design an energy efficient 12-bit noise shaping (NS) successive-approximation register (SAR) ADC. The 2nd-order noise shaping architecture with multiple feed-forward paths is adopted and analyzed to optimize system design parameters. By utilizing tunnel field effect transistors (TFETs), the Delta-Sigma SAR is realized under an ultra-low supply voltage VDD with high energy efficiency. The stochastic neuron is a key for event-based probabilistic neural networks. We propose a stochastic neuron using a metal-oxide resistive random-access memory (ReRAM). The ReRAM\u27s conducting filament with built-in stochasticity is used to mimic the neuron\u27s membrane capacitor, which temporally integrates input spikes. A capacitor-less neuron circuit is designed, laid out, and simulated. The output spiking train of the neuron obeys the Poisson distribution. Based on the ReRAM based neuron, we propose a scalable and reconfigurable architecture that exploits the ReRAM-based neurons for deep Spiking Neural Networks (SNNs). In prior publications, neurons were implemented using dedicated analog or digital circuits that are not area and energy efficient. In our work, for the first time, we address the scaling and power bottlenecks of neuromorphic architecture by utilizing a single one-transistor-one-ReRAM (1T1R) cell to emulate the neuron. We show that the ReRAM-based neurons can be integrated within the synaptic crossbar to build extremely dense Process Element (PE)–spiking neural network in memory array–with high throughput. We provide microarchitecture and circuit designs to enable the deep spiking neural network computing in memory with an insignificant area overhead

High-Speed Radhard Mega-Pixel CIS Camera for High-Energy Physics

This dissertation describes the schematic design, physical layout implementation, system-level hardware with FPGA firmware design, and testing of a camera-on-a-chip with a novel high-speed CMOS image sensor (CIS) architecture developed for a mega-pixel array. The novel features of the design include an innovative quadruple column-parallel readout (QCPRO) scheme with rolling shutter that increases pixel rate, its ability to program the frame rate and to tolerate Total Ionizing Dose effects (TID). Two versions of the architecture, a small (128 x 1,024 pixels) and large (768 x 1,024 pixels) version were designed and fabricated with a custom layout that does not include library parts. The designs achieve a performance of 20 to 4,000 frames per second (fps) and they tolerate up to 125 krads of radiation exposure. The high-speed CIS architecture proposes and implements a creative quadruple column-parallel readout (QCPRO) scheme to achieve a maximum pixel rate, 10.485 gigapixels/s. The QCPRO scheme consists of four readout blocks per column and to complete four rows of pixels readout process at one line time. Each column-level readout block includes an analog time-interleaving (ATI) sampling circuit, a switched-capacitor programmable gain amplifier (SC-PGA), a 10-bit successive-approximation register (SAR) ADC, two 10-bit memory banks. The column-parallel SAR ADC is area-efficient to be laid out in half of one pixel pitch, 10 um. The analog ATI sampling circuit has two sample-and-hold circuits. Each sampling circuit can independently complete correlated double sampling (CDS) operation. Furthermore, to deliver over 10^10 pixel data in one second, a high-speed differential Scalable Low-Voltage Signaling (SLVS) transmitter for every 16 columns is designed to have 1 Gbps/ch at 0.4 V. Two memory banks provide a ping-pong operation: one connecting to the ADC for storing digital data and the other to the SLVS for delivering data to the off-chip FPGA. Therefore, the proposed CIS architecture can achieve 10,000 frames per second for a 1,024 x 1,024 pixel array. The floor plan of the proposed CIS architecture is symmetrical having one-half of pixel rows to read out on top, and the other half read out on the bottom of the pixel array. The rolling shutter feature with multi-lines readout in parallel and oversampling technique relaxes the image artifacts for capturing fast-moving objects. The CIS camera can provide complete digital input control and digital pixel data output. Many other components are designed and integrated into the proposed CMOS imager, including the Serial Peripheral Interface (SPI), bandgap reference, serializers, phase-locked loops (PLLs), and sequencers with configuration registers. Also, the proposed CIS can program the frame rate for wider applications by modifying three parameters: input clock frequency, the region of interest, and the counter size in the sequencer. The radiation hardening feature is achieved by using the combination of enclosed geometry technique and P-type guard-rings in the 0.18 um CMOS technology. The peripheral circuits use P-type guard-rings to cut the TID-induced leakage path between device to device. Each pixel cell is radiation tolerant by using enclosed layout transistors. The pinned photodiode is also used to get low dark current, and correlated double sampling to suppress pixel-level fixed-pattern noise and reset noise. The final pixel cell is laid out in 20 x 20 um^2. The total area of the pixel array is 2.56 x 20.28 mm^2 for low-resolution imager prototype and 15.36 x 20.28 mm^2 for high-resolution imager prototype. The entire CIS camera system is developed by the implementation of the hardware and FPGA firmware of the small-format prototype with 128 x 1,024 pixels and 754 pads in a 4.24 x 25.125 mm^2 die area. Different testing methods are also briefly described for different test purposes. Measurement results validate the functionalities of the readout path, sequencer, on-chip PLLs, and the SLVS transmitters. The programmable frame rate feature is also demonstrated by checking the digital control outputs from the sequencer at different frame rates. Furthermore, TID radiation tests proved the pixels can work under 125 krads radiation exposure