The Impact of Externally Applied Mechanical Stress on Analog and RF Performances of SOI MOSFETs, Journal of Telecommunications and Information Technology, 2009, nr 4

This paper presents a complete study of the impact of mechanical stress on the performance of SOI MOSFETs. This investigation includes dc, analog and RF characteristics. Parameters of a small-signal equivalent circuit are also ex- tracted as a function of applied mechanical stress. Piezoresistance coefficientis shown to be a key element in describing the enhancement in the characteristics of the device due to mechanical stress

Device physics and failure mechanisms of deep submicron gate GaN HEMTs for microwave and millimeter-wave applications

openThis thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs.This thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs

Local characterisation of strain in silicon nanostructures

PhD ThesisStrain engineering is used in the microelectronics industry for fabricating micro- and nano-electromechanical systems (MEMS and NEMS) and state-of-the-art metal-oxide-semiconductor field-effect transistors (MOSFETs). In these devices suspended silicon beams, films and nanowires are widely used. However, the mechanical, thermal and electrical properties of silicon change significantly at the nanoscale. Therefore, an accurate knowledge of the size effect on these properties, the role of the surface and an accurate characterisation of the stress and strain distribution in these devices is needed for a complete understanding of the device operation. Likewise, state-of-the-art MOSFETs incorporate strain into the channel to improve performance due to a carrier mobility enhancement compared with unstrained silicon channel transistors. However, the mobility enhancement especially at high vertical electric fields (where commercial MOSFETs operate), is still not well understood. The SiO2/Si interface roughness exhibits, at the nanoscale, scaling behaviour with the scale of observation. However, to date, there is no experimental study of the SiO2/Si interface roughness scaling behaviour with strain. This study is needed to better understand the surface roughness scattering-limited mobility of electrons and holes in strained devices. Raman spectroscopy is a widely used technique to characterise strain. However, the conversion of Raman peak shifts to strain values requires a strain-shift coefficient. Traditionally, the reported strain-shift coefficients have been determined from experiments performed in bulk material. The applied stress has also been limited within the range 0 – 2 GPa. This range is reasonable for bulk silicon characterisation but is too narrow for silicon nanostructures and devices where higher stress values are often favourable for improving performance. Consequently, there is an outstanding need to find appropriate strain-shift coefficients for silicon nanowires and thin films under large values of stress. In this thesis strain in silicon nanostructures is experimentally and theoretically investigated for strain values ranging from 0 to 3.6%. Strain has been characterised using scanning electron microscopy (SEM), Raman spectroscopy, and theoretically with analytical calculations and finite element simulations. The combination of these techniques and the large number of samples (up to 85) has allowed the accurate determination of the ii strain-shift coefficient for the technologically important (100) silicon surface and for stress values up to 4.5 GPa. The work also enables a better understanding of the changes in silicon properties with strain when device dimensions are reduced to the nanoscale. The size dependency of the Young‟s modulus, fracture strain, thermal conductivity and the role of the surface in the size dependent physics are also investigated. It is found that some properties such as the fracture strain change with the dimensions of the sample whereas others such as the Young‟s modulus and thermal conductivity do not change. Finally, the impact of uniaxial and biaxial strain on the surface roughness of silicon nanostructures and thin films has been analysed by atomic force microscopy (AFM). It is found that the silicon surface roughness changes in different manner with uniaxial and biaxial strain. The results show that the silicon surface roughness is self-affine with strain and that this behaviour has to be considered within the models used to describe the carrier mobility in MOSFETs at high vertical electric fields.Engineering and Physical Sciences Research Council (EPSRC) HORIBA Jobin Yvon Ltd

Managing Variability in VLSI Circuits.

Over the last two decades, Design for Manufacturing (DFM) has emerged as an essential field within the semiconductor industry. The main objective of DFM is to reduce and, if possible, eliminate variability in integrated circuits (ICs). Numerous techniques for managing variation have emerged throughout IC design: manufacturers design instruments with minute tolerances, process engineers calibrate and characterize a given process throughout its lifetime, and IC designers strive to model and characterize variability within their devices, libraries, and circuits. This dissertation focuses on the last of these three techniques and presents material relevant to managing variability within IC design. Since characterization and modeling are essential to the analysis and reduction of variation in modern-day designs, this dissertation begins by studying various correlation models used within Statistical Static Timing Analysis (SSTA). In the end, the study shows that using complex correlation models does not necessarily result in significant error reduction within SSTA, and that simple models (which only include die-to-die and random variation) can therefore be used to achieve similar accuracy with reduced overhead and run-time. Next, the variation models, themselves, are explored and a new critical dimension (CD) model is proposed which reduces standard deviation error in SSTA by ~3X. Finally, the focus changes from the timing analysis level and moves lower in the design hierarchy to the libraries and devices that comprise the backbone of IC design. The final three chapters study mechanical stress enhancement and discuss how to fully exploit the layout dependencies of mechanically stressed silicon. The first of these three chapters presents an optimization scheme that uses the layout dependencies of stress in conjunction with dual-threshold-voltage (Vth) assignment to decrease leakage power consumption by ~24%. Next, the second of the three chapters proposes a new standard cell library design methodology, called “STEEL.” STEEL provides average delay improvements of 11% over equivalent single-Vth implementations, while consuming 2.5X less leakage than the dual-Vth alternative. Finally, the stress enhanced studies (and this document) are concluded by a new optimization scheme that combines stress enhancement with gate length biasing to achieve 2.9X leakage power savings in IC designs without modifying Vth.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75947/1/btcline_1.pd

Advanced Silicon and Germanium Transistors for Future P-channel MOSFET Applications

Ph.DDOCTOR OF PHILOSOPH

Nanoscale characterisation of dielectrics for advanced materials and electronic devices

PhD ThesisStrained silicon (Si) and silicon-germanium (SiGe) devices have long been recognised for their enhanced mobility and higher on-state current compared with bulk-Si transistors. However, the performance and reliability of dielectrics on strained Si/strained SiGe is usually not same as for bulk-Si. Epitaxial growth of strained Si/SiGe can induce surface roughness. The typical scale of surface roughness is generally higher than bulk-Si and can exceed the device size. Surface roughness has previously been shown to impact the electrical properties of the gate dielectric. Conventional macroscopic characterisation techniques are not capable of studying localised electrical behaviour, and thus prevent an understanding of the influence of large scale surface roughness. However scanning probe microscopy (SPM) techniques are capable of simultaneously imaging material and electrical properties. This thesis focuses on understanding the relationship between substrate induced surface roughness and the electrical performance of the overlying dielectric in high mobility strained Si/SiGe devices. SPM techniques including conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been applied to tensile strained Si and compressively strained SiGe materials and devices, suitable for enhancing electron and hole mobility, respectively. Gate leakage current, interface trap density, breakdown behaviour and dielectric thickness uniformity have been studied at the nanoscale. Data obtained by SPM has been compared with macroscopic electrical data from the same devices and found to be in good agreement. For strained Si devices exhibiting the typical crosshatch morphology, the electrical performance and reliability of the dielectric is strongly influenced by the roughness. Troughs and slopes of the crosshatch morphology lead to degraded gate leakage and trapped charge at the interface compared with peaks on the crosshatch undulations. Tensile strained Si material which does not exhibit the crosshatch undulation exhibits improved uniformity in dielectric properties. Quantitative agreement has been found for leakage at a device-level and nanoscale, when accounting for the tip area. The techniques developed can be used to study individual defects or regions on dielectrics whether grown or deposited (including high-κ) and on different substrates including strained Si on insulator (SSOI), strained Ge on insulator (SGOI), strained Ge, silicon carbide (SiC) and graphene. Strained SiGe samples with Ge content varying from 0 to 65% have also been studied. The increase in leakage and trapped charge density with increasing Ge extracted from SPM data is in good agreement with theory and macroscopic data. The techniques appear to be very sensitive, with SCM analysis detecting other dielectric related defects on a 20% Ge sample and the effects of the 65% Ge later exceeding the critical thickness (increased defects and variability in characteristics). Further applications and work to advance the use of electrical SPM techniques are also discussed. These include anti-reflective coatings, synthetic chrysotile nanotubes and sensitivity studies.Overseas Research Students Awards Scheme (ORSAS), School International Research Scholarship (SIRS), Newcastle University International Postgraduate Scholarship (NUIPS) and the Strained Si/SiGe platform grant

Journal of Telecommunications and Information Technology, 2009, nr 4

kwartalni

Ouyang, Strain for CMOS performance improvement

Abstract Device Improvement with strain engineering is considered a way to enhance the carrier mobility. Several stress-transfer techniques (such as etch-stop liner, stress transfer technique, e-SiGe) using extra integration process into an existing baseline process is demonstrated. In addition, new preparation techniques of strained-Si surface (e.g. biaxial tensile stress) and different substrate orientation to enhance mobility are introduced. The challenges and vitality of each method will be discussed and compared. In addition, we will highlight how the stress oriented from the layout geometry affects the device electrical behavior. The issues and improvement in the circuit level device modeling will be discussed