Caractérisation électrique de transistors à effet de champ avancés : transistors sans jonctions, sur réseaux de nanotubes de carbone ou sur nanofil en oxyde d'étain

In this dissertation, the electrical characterization of heavily-doped junctionless transistors (JLTs) and individual tin-oxide (SnO2) nanowire field-effect transistors (FETs) and single-walled carbon nanotube (SWCNT) random network thin film transistors (RN-TFTs) are presented in terms of I-V, C-V, low frequency noise (LFN), and low temperature measurement including a numerical simulation, respectively. As a potential emerging candidate for more than Moore, recently developed heavily doped JLTs were studied in low-temperature (77K ~ 350K) with double gate mode to have physical insights of carrier scattering mechanism with account for both the position of flat-band voltage and doping concentration, respectively. Besides, as a nano-scaled bottom-up device, polymethyl methacrylate passivated individual SnO2 nanowire FET was discussed. A large contribution of channel access resistance to carrier mobility and LFN behavior was found as same as in nano-structure devices. Furthermore, various electrical characteristics of percolation dominant N-type SWCNT RN-TFTs were demonstrated by taking into account for I-V, C-V, LFN and a numerical percolation simulation.Les matériaux de faible dimensionnalité, tels que les nanotubes de carbone, le graphène, les nanofils de semi-conducteurs ou d'oxydes métalliques, présentent des propriétés intéressantes telles qu'un rapport surface/ volume important, des mobilités électroniques élevées, des propriétés thermiques et électriques particulières, avec la possibilité de constituer une alternatives à certaines fonctions CMOS ou d'intégrer de nouvelles fonctions comme la récupération d'énergie ou des capteurs. Pour la bio-détection, les nanofils permettent par exemple d'obtenir une grande sensibilité à la présence de biomolécules cibles grâce à la modification de charge qui accompagne leur hybridation sur des biomolécules sondes greffées à la surface du nanofil et au fort couplage électrostatique de cette charge de surface avec le cœur du nanofil. La fabrication de ce type de structure suit différentes voies: une voie dite "top-down" qui est utilisée par la production microélectronique de masse et qui permet un excellent contrôle technologique grâce à l'utilisation d'équipements, notamment de lithographie, extrêmement performants; une seconde voie moins coûteuse mais moins contrôlée dite "bottom-up" dont un exemple répandu est la réalisation de réseaux aléatoires, obtenus par dispersion de nanostructures réalisées directement sous forme 1D par croissance et en général relativement dopés de façon non nécessairement contrôlée. Dans les deux cas, le mécanisme de base est le contrôle électrostatique du canal par effet de champ d'un ensemble (organisé ou non) de nanostructures. Dans cette thèse, trois types de transistors différents sont explorées ; des transistors à nanofils SnO2, des réseaux aléatoires de nanotubes de carbone, des transistors à nanofil à canal uniformément dopé, dits "junctionless transistors" ou JLTs). Par rapport à la configuration classique d'un transistor MOS à inversion, le contrôle demande en général à être reconsidéré pour tenir compte des spécificités de ce type de structures: topologie du canal, isolants non standards (résines), effets de percolation dans les réseaux désordonné, contrôle électrostatique dans les nanofils fortement dopés, rôle crucial des états d'interface. Le travail s'appuie sur (i) une caractérisation approfondie de ces composants en statique (contrôle du courant), en petit signal (contrôle de la charge) et en bruit (pièges et états d'interfaces), (ii) une analyse critique des méthodologies d'extraction de paramètres et des modèles utilisés pour analyser ce fonctionnement avec dans certains cas l'appui de simulations et (iii) le développement, lorsque cela s'avère nécessaire, de nouvelles méthodologies d'extraction

Novel solution processable dielectrics for organic and graphene transistors

In this thesis we report the development of a range of high-performance thin-film transistors utilising different solution processable organic dielectrics grown at temperatures compatible with inexpensive substrate materials such as plastic. Firstly, we study the dielectric properties and application of a novel low-k fluoropolymer dielectric, named Hyflon AD (Solvay). The orthogonal nature of the Hyflon formulation, to most conventional organic semiconductors, allows fabrication of top-gate transistors with optimised semiconductor/dielectric interface. When used as the gate dielectric in organic transistors, this transparent and highly water-repellent polymer yields high-performance devices with excellent operating stability. In the case of top-gate organic transistors, hole and electron mobility values close to or higher than 1 cm2/Vs, are obtained. These results suggest that Hyflon AD is a promising candidate for use as dielectric in organic and potentially hybrid electronics. By taking advantage of the non-reactive nature of the Hyflon AD dielectric, the p-doping process of an organic blend semiconductor using a molybdenum based organometallic complex as the molecular dopant, has also been investigated for the first time. Although the much promising properties of Hyflon AD were demonstrated, the resulting transistors need, however, to be operated at high voltages typically in the range of 50-100 V. The latter results to a high power consumption by the discrete transistors as well as the resulting integrated circuits. Therefore, reduction in the operating voltage of these devices is crucial for the implementation of the technology in portable battery-operated devices. Our approach towards the development of low-voltage organic transistors and circuits explored in this work focused on the use of self-assembled monolayer (SAM) organics as ultra-thin gate dielectrics. Only few nanometres thick (2-5 nm), these SAM dielectrics are highly insulating and yield high geometrical capacitances in the range 0.5 - 1 μF/cm2. The latter has enabled the design and development of organic transistors with operating voltages down to a few volts. Using these SAM nanodielectrics high performance transistors with ambipolar transport characteristics have also been realised and combined to form low-voltage integrated circuits for the first time. In the final part of this thesis the potential of Hyflon AD and SAM dielectrics for application in the emerging area of graphene electronics, has been explored. To this end we have employed chemical vapour deposited (CVD) graphene layers that can be processed from solution onto the surface of the organic dielectric (Hyflon AD, SAM). By careful engineering of the graphene/dielectric interface we were able to demonstrate transistors with improved operating characteristics that include; high charge carrier mobility (~1400 cm2/Vs), hysteresis free operation, negligible unintentional doping and improved reliability as compared to bare SiO2 based devices. Importantly, the use of SAM nanodielectrics has enabled the demonstration of low voltage (<|1.5| V) graphene transistors that have been processed from solution at low temperature onto flexible plastic substrates. Graphene transistors with tuneable doping characteristics were also demonstrated by taking advantage of the SAM’s flexible chemistry and more specifically the type of the chemical SAM end-group employed. Overall, the work described in this thesis represents a significant step towards flexible carbon-based electronics where large-volume and low-temperature processing are required

Conducting metal oxide materials for printed electronics

Printed electronics as a manufacturing process has many advantages, mainly, it allows for the high throughput rapid fabrication of thin, flexible electronic components with minimal waste. There are many printing processes that can be utilised for printing electronics and although each process can differ vastly, the materials currently used in these processes are generally the same, silver and carbon. However, to develop printing as a more mainstream manufacturing method for electronics, a wider variety of materials are required which can provide better stability and longevity of components, new functionality for printed applications and allow for in-situ processing and tuning of components. Conducting metal oxides are a good candidate for integrating into printed electronics processes, these materials are typically semiconductors, they have bandgaps, and properties can be altered via altering the band gap. They are also oxides, so they cannot oxidise further and therefore atmospheric damage is reduced compared to pure metals. They can also be fabricated into a wide range of particle morphologies, all with advantages in different fields and electronic applications. Therefore, the ability to print these materials is valuable to the field. In this thesis, the integration of conducting metal oxide electro-ceramic materials into the field of printed electronics has been explored. This was performed through the completion of five research objectives including, the selection of appropriate materials for the research, the formulation of conductive inks with the materials, the investigation of post-processing techniques for printed films and further research into passive component fabrication and sensor applications. Firstly, following an extensive literature review, four materials were selected including three doped zinc oxide materials synthesised via different methods. The fourth material is commercially sourced indium tin oxide (ITO). A nitrocellulose vehicle was determined to be the most compatible with the oxides and selected for ink formulation. Inks were then formulated with all four materials, with optical and electrical properties analysed. Gallium doped Zinc Oxide (GZO) and ITO were selected for further investigation based on the excellent conductivity of the indium tin oxide (57.77Ω□-1) and the highly transparent optical properties of the gallium doped zinc oxide (>84% transmittance). Laser processing was selected as a post processing method. It was found that the laser processing dramatically increased conductivity. The GZO improving from a non-conductive film to 10.21% of bulk conductivity. The ITO improved from 3.46% to 40.47% of the bulk conductivity. It was also found that the laser processing invoked a carbothermal reduction process allowing for a rapid manufacturing process for converting spherical particles into useful nanoparticle morphologies (nanorods, nanowires etc). Following this, resistive and capacitive applications involving laser processing and conventionally heat-treated conductive oxide inks were developed. Combining the new materials and manufacturing processes, tuneable printed resistors with a tuning range of 50 to 20M could be fabricated. All metal oxide, ITO based capacitors were also fabricated and characterised. These were then developed into humidity sensors which provided excellent humidity sensing properties, showing linearity between 5 and 95% relative humidity (RH) and sensitivities of up to 7.76pF/RH%, demonstrating higher performance than commercial equivalents (0.2 – 0.5pF/RH%). In conclusion, this work provides a breakthrough for conductive metal oxide materials research and its place in Printed Electronics research by providing insight into the processes required to make these materials conduct and by developing useful manufacturing methods, post processing techniques and applications.</div

Wetting and phase-change phenomena on micro/nanostructures for enhanced heat transfer

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, February 2013.Page 76 blank. Cataloged from PDF version of thesis.Includes bibliographical references (p. 71-75).Micro/nanostructures have been extensively studied to amplify the intrinsic wettability of materials to create superhydrophilic or superhydrophobic surfaces. Such extreme wetting properties can influence the heat transfer performance during phase-change which is of great importance in a wide range of applications including thermal management, building environment, water harvesting and power production. In particular, superhydrophilic surfaces have been of interest to achieve thin film evaporation with high heat fluxes. Meanwhile, superhydrophobic surfaces with dropwise condensation promises higher heat transfer coefficients than typical filmwise condensation. My thesis work aims at improving fundamental understanding as well as demonstrating practical enhancements in these two areas. A key challenge to realizing thin film evaporation is the ability to achieve efficient fluid transport using superhydrophilic surfaces. Accordingly, we developed a semi-analytical model based on the balance between capillary pressure and viscous resistance to predict the propagation rates in micropillar arrays with high aspect ratios. Our experimental results showed good agreement with the model, and design guidelines for optimal propagation rates were proposed. For micropillar arrays with low aspect ratio and large spacing between pillars, however, we identified that the microscopic sweeping of the liquid front becomes important. We studied this phenomenon, explained the effect of such microscale dynamics on the overall propagation behavior, and proposed a strategy to account for these dynamics. While these propagation studies provide a means to deliver liquid to high heat flux regions, we investigated a different configuration using nanoporous membrane that decouples capillarity from the viscous resistance to demonstrate the potential heat dissipation capability. With nanoporous membranes with average pore diameters of 150 nm and thicknesses of 50 [mu]m, we achieved interfacial heat fluxes as high as 96 W/cm2 via evaporation with isopropyl alcohol. The effect of membrane thickness was studied to offer designs that promise dissipation of 1000 W/cm 2 . Meanwhile, we developed new metrology to measure transient heat transfer coefficients with a temporal resolution of 0.2 seconds during the evaporation process. Such a technique offers insight into the relationship between liquid morphology and heat transfer behavior. Finally, for enhanced condensation, we demonstrated immersion condensation using a composite surface fabricated by infusing hydrophobic oil into micro/nanostructures with a heterogeneous coating. With this approach, three key attributes to maximize heat transfer coefficient, low departure radii, low contact angle, and high nucleation density, were achieved simultaneously. We specifically elucidated the mechanism for the increase in nucleation density and attribute it to the combined effect of reduced water-oil interfacial energy and local high surface energy sites. As a result, we demonstrated approximately 100% enhancement in heat transfer coefficient over state-of-the-art superhydrophobic surfaces with the presence of non-condensable gases. This thesis presents improved fundamental understanding of wetting, evaporation, and condensation processes on micro/nanostructures as well as practical implementation of these structures for enhanced heat transfer. The insights gained demonstrate the potential of new nanostructure engineering approaches to improve the performance of various thermal management and energy production applications.by Rong Xiao.Ph.D

Caractérisation électrique de transistors sans jonctions avec simulation numérique

L'invention du premier transistor à Bell lab's, dans le groupe de W. Shockley, en 1947 a été suivie d'une ère de développement des circuits intégrés (IC). Depuis plusieurs dizaines d'années, la dimension critique des transistors métal/oxyde/semi-conducteurs (les transistors MOS), la longueur physique de la grille, a diminué à un rythme régulier. Cette évolution, motivée par des raisons économiques, a été anticipée par G. Moore, et est de ce fait connue sous le nom de "loi de Moore". La dimension de grille a d'ores et déjà été réduite de plus de 2 ordres de grandeur et, dans son édition2012, l'association ITRS prédit qu'elle décroîtra encore, de 22nm en 2011 à environ 6nm en 2026 [1].Toutefois, cette réduction des dimensions fait apparaître un certain nombre d'effets secondaires qui altèrent le fonctionnement idéal des transistors MOS [2].In this dissertation, the performance of junction less transistors (JLTs) as possible candidates for the continuation of Moore s law was investigated experimentally based on an in-depth study of their electrical characteristics. Current-voltage I-V and capacitance-voltage C-V were analyzed in a wide rangeof temperatures (from 80 K to 350 K) in correlation with device operation mechanism. Lowfrequencynoise was also studied and compared to that of inversion-mode transistors. This study requirednew parameter extraction methods to be defined for JLTs. Their validity was confirmed by 2-dimensional (2D) simulation results. They will be detailed in this dissertation.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Development and characterization of micro/nano structured surfaces for enhanced condensation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 159-168).Micro/nanostructures have long been recognized to have potential for heat transfer enhancement in phase-change processes by achieving extreme wetting properties, which is of great importance in a wide range of applications including thermal management, building environment control, water harvesting, desalination, and industrial power generation. This thesis focuses on the fundamental understanding of water vapor condensation on superhydrophobic surfaces, as well as the demonstration of such surfaces for enhanced condensation heat transfer performance. We first studied droplet-surface interactions during condensation on superhydrophobic surfaces to understand the emergent droplet wetting morphology. We demonstrated the importance of considering local energy barriers to understand the condensed droplet morphologies and showed nucleation-mediated droplet-droplet interactions can overcome these barriers to develop wetting states not predicted by global thermodynamic analysis. To minimize these droplet-droplet interactions and ensure the formation of favorable morphologies for enhanced condensation heat transfer, we show that the structure length scale needs to be minimized while ensuring the local energy barriers satisfy the morphology dependent criteria. This mechanistic understanding offers insight into the role of surface-structure length scale and provides a quantitative basis for designing surfaces optimized for condensation in engineered systems. Using our understanding of emergent droplet wetting morphology, we experimentally and numerically investigated the morphology dependent individual droplet growth rates. By taking advantage of well-controlled functionalized silicon nanopillars, the growth and shedding behavior of both suspended and partially wetting droplets on the same surface during condensation was observed. Environmental scanning electron microscopy was used to demonstrate that initial droplet growth rates of partially wetting droplets were 6 times larger than that of suspended droplets. A droplet growth model was developed to explain the experimental results and showed that partially wetting droplets had 4-6 times higher heat transfer rates than that of suspended droplets. Based on these findings, the overall performance enhancement created by surface nanostructuring was examined in comparison to a flat hydrophobic surface. These nanostructured surfaces had 56% heat flux enhancement for partially wetting droplet morphologies, and 71% heat flux degradation for suspended morphologies in comparison to flat hydrophobic surfaces. This study provides fundamental insights into the previously unidentified role of droplet wetting morphology on growth rate, as well as the need to design nanostructured surfaces with tailored droplet morphologies to achieve enhanced heat and mass transfer during dropwise condensation. To create a unified model for condensation capable of predicting the surface heat transfer for a variety of surface length scales, geometries, and condensation conditions, we incorporated the emergent droplet wetting morphology, individual droplet heat transfer, and size distribution. The model results showed a specific range of characteristic length scales (0.5 - 2 ptm) allowing for the formation of coalescence-induced jumping droplets with a 190% overall surface heat flux enhancement over conventional flat dropwise condensing surfaces. This work provided a unified model for dropwise condensation on micro/nanostructured superhydrophobic surfaces and offered guidelines for the selection of ideal structured surfaces to maximize heat transfer. Using the insights gained from the developed model and optimization, a scalable synthesis technique was developed to produce functionalized oxide nanostructures on copper surfaces capable of sustaining superhydrophobic condensation. Nanostructured copper oxide (CuO) films were formed via chemical oxidation in an alkaline solution resulting in dense arrays of sharp CuO nanostructures with characteristic heights and widths of -1 pm and -300 nm, respectively. Condensation on these surfaces was characterized using optical microscopy and environmental scanning electron microscopy to quantify the distribution of nucleation sites and elucidate the growth behavior of individual droplets with characteristic radii of -1 to 10 pm at supersaturations < 1.5. Comparison of the measured individual droplet growth behavior showed good agreement with our developed heat transfer model. We subsequently studied the macroscopic heat transfer performance during water condensation on superhydrophobic CuO tube surfaces in a custom built experimental chamber. The results experimentally demonstrated for the first time a 25% higher overall heat flux and 30% higher condensation heat transfer coefficient compared to state-of-the-art hydrophobic condensing surfaces at low supersaturations (<1.12). This work not only shows significant condensation heat transfer enhancement, but promises a low cost and scalable approach to increase efficiency for applications such as atmospheric water harvesting and dehumidification. Furthermore, the results offer insights and an avenue to achieve high flux superhydrophobic condensation. In addition to demonstrating enhanced heat transfer performance, we discovered electrostatic charging of jumping droplets on CuO. With the aid of electric fields, the charge on the droplets was quantified, and the mechanism for the charge accumulation was studied. We demonstrated that droplet charging was associated with the formation of the electric double layer at the droplet-surface interface, and subsequent separation during coalescence and jumping. The observation of droplet charge accumulation and electric double layer charge separation provides important insight into jumping droplet physics. Furthermore, this work is a starting point for more advanced approaches for enhancing jumping droplet surface performance by using external electric fields to control droplet jumping. Finally, we demonstrated electric-field-enhanced (EFE) condensation, whereby an external electric field was used to force charged departing droplets away from the surface and limit their return. With the CuO surfaces, we studied EFE condensation heat transfer performance during water condensation. The results experimentally demonstrated a 50% higher overall heat transfer coefficient compared to the no-field jumping surface at low supersaturations (<1.12). This work not only shows significant condensation heat transfer enhancement, it offers insights into new avenues for improving the performance of self-cleaning and anti-icing surfaces, as well as thermal diodes. This thesis presents improved fundamental understanding of wetting and condensation on micro/nanostructures as well as practical implementation of these structures for enhanced condensation heat transfer. The insights gained demonstrate the potential of new surface engineering approaches to improve the performance of various thermal management and energy production applications.by Nenad Miljkovic.Ph.D

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.Peer ReviewedPostprint (published version

Caractérisation électrique des propriétés d'interface dans les MOSFET nanométriques par des mesures de bruit basse fréquence

In this thesis, electrical properties of gate oxide/channel interface in ultra-scaled nanowire (NW) MOSFETs were experimentally investigated by carrier transport and low-frequency noise (LFN) characterizations. NW FETs, which have aggressively downscaled cross-section of the body, are strong candidates for near future CMOS node. However, the interface quality could be a critical issue due to the large surface/volume ratio, the multiple surface orientations, and additional strain technology to enhance the performance. Understanding of carrier transport and channel interface quality in NW FETs with advanced high-k/metal gate is thus particularly important. LFN provides deep insights into the interface properties of MOSFET without lower limit of required channel size. LFN measurement thus can be a powerful technique for ultra-scaled NW FETs. Also, fitting mobility (such as low-field mobility) extraction by Y-function method is an efficient method. Omega-gate NW FETs were fabricated from FD-SOI substrates, and with Hf-based high-k/metal gate (HfSiON/TiN), reducing detrimental effects by device downscaling. In addition, strain technologies to the channel were additively processed. Tensile strained-SOI substrate was used for NMOS, whereas compressive stressors were used for PMOS devices. Strained Si channel for PMOS was processed by raised SiGe S/D and CESL formations. Strained SiGe channel (SGOI) was also fabricated for further high-performance PMOS FETs. Firstly, the most common Id-Vg was characterized in single-channel NW FETs as the basic performance. Reference SOI NWs provided the excellent static control down to short channel of 17nm. Stressors dramatically enhanced on-current owing to a modification of channel energy-band structure. Then, extracted low-field mobility in NWs also showed large improvement of the performance by stressors. The mobility extraction effectively evaluated FET performance even for ultra-scaled NWs. Next, LFN investigated for various technological and architectural parameters. Carrier number fluctuations with correlated mobility fluctuations (CNF+CMF) model described 1/f noise in all our FETs down to the shortest NWs. Drain current noise behavior was basically similar in both N- and PMOS FETs regardless of technological splits. Larger 1/f noise stemming from S/D regions in PMOS FETs was perfectly interpreted by the CNF+CMF model completed with Rsd fluctuations. This observation highlighted an advantage of SGOI NW with the lowest level of S/D region noise. Geometrical variations altered the CNF component with simple impact of device scaling (reciprocal to both Wtot and Lg). No large impact of surface orientation difference between the channel (100) top and (110) side-walls in [110]-oriented NWs was observed. Scaling regularity with both Wtot and Lg, without much quantum effect, could be attributed to the use of HfSiON/TiN gate and carrier transport occurring mostly near top and side-wall surfaces even in NW geometry. Meanwhile, the CMF factor was not altered by decreasing dimensions, while the mobility strongly depends on the impact. Extracted oxide trap density was roughly steady with scaling, structure, and technological parameter impacts. Simple separation method of the contributions between channel top surface and side-walls was demonstrated in order to evaluate the difference. It revealed that oxide quality on (100) top and (110) side-walls was roughly comparable in all the [110]-devices. The density values lie in similar order as the recent reports. An excellent quality of the interface with HfSiON/TiN gate was thus sustained for all our technological and geometrical splits. Finally, our NWs fulfilled 1/f LFN requirements stated in the ITRS 2013 for future MG CMOS logic node. Consequently, we concluded that appropriate strain technologies powerfully improve both carrier transport and LFN property for future CMOS circuits consisting of NW FETs, without any large concern about the interface quality.Dans cette thèse, les propriétés électriques de transistors à nanofils de silicium liées à l'interface oxyde de grille/canal ont été étudiées par le biais de mesures de bruit basse fréquence (bruit 1/f) et de transport dans le canal. Ces transistors nanofils dont les dimensions ont été réduites jusqu'à quelques nanomètres pour la section, représentent une alternative sérieuse pour les futurs nœuds technologiques CMOS. Cependant, la qualité de l'interface oxyde de grille/canal pose question pour transistors dont l'architecture s'étend dans les 3 dimensions, en raison du fort rapport surface/volume inhérent à ces transistors, des différentes orientations cristallographiques de ces interfaces, ou encore des matériaux contraints utilisés pour améliorer les performances électriques. La compréhension des liens entre les propriétés de transport des porteurs dans le canal, qui garantissent en grande partie les performances électriques des transistors, et la qualité de l'interface avec l'oxyde de grille est fond primordiale pour optimiser les transistors nanofils. Les mesures de bruit, associées à l'étude du transport dans le canal, sont un outil puissant et adapté à ces dispositifs tridimensionnels, sans être limité par la taille ultra-réduite des transistors nanofils. Les transistors nanofils étudiés ont été fabriqués à partir de substrats minces SOI, et intègrent un empilement de grille HfSiON/TiN, qui permet de réduire les dimensions tout en conservant les mêmes propriétés électrostatiques. Pour gagner en performances, des contraintes mécaniques ont été introduites dans le canal en silicium : en tension pour les NMOS, par le biais de substrat contraint (sSOI), et en compression pour les PMOS. Un canal en compression uni-axiale peut être obtenu par l'intégration de source/drain en SiGe et/ou par l'utilisation de couches contraintes de type CESL. Des transistors à canal SiGe sur isolant en compression ont également été fabriqués et étudiés. Les caractéristiques électriques des divers transistors nanofils (courbes Id-Vg, compromis Ion-Ioff, mobilité des porteurs) démontrent l'excellent contrôle électrostatique dû à l'architecture 3D, ainsi que l'efficacité de l'ingénierie de contraintes dans les nanofils jusqu'à de faibles longueurs de grilles (~17nm). Des mesures de bruit basse fréquence ont été réalisées sur ces mêmes dispositifs et analysées en fonction des paramètres géométriques de l'architecture nanofils (largeur W, forme de la section, longueur de grille L), et des diverses variantes technologiques. Nous avons démontré que le bruit 1/f dans les transistors nanofils peut être décrit par le modèle de fluctuations du nombre de porteurs (CNF) corrélées aux fluctuations de mobilité (CMF). Le bruit associé aux régions S/D a pu également être intégré dans ce modèle en ajoutant une contribution, en particulier pour les PMOS. Alors que les différentes variantes technologiques ont peu d'effet sur le bruit 1/f, les variations de géométrie en L et W changent la composante de bruit liée aux fluctuations du nombre de porteurs (CNF) de manière inversement proportionnelle à la surface totale (~1/WL). Cette augmentation du bruit est le reflet du transport qui se produit à proximité des interfaces avec l'oxyde. Les différentes orientations des interfaces supérieures et latérales (110) ou (100) présentent la même quantité de pièges d'interface (extrait à partir des mesures de bruit 1/f, en séparant les contributions des différentes faces du nanofil) bien qu'ayant une rugosité différente essentiellement liée au process. En revanche la composante CMF n'est pas altérée par la réduction des dimensions contrairement à la mobilité des porteurs qui décroit fortement avec L. Finalement, les mesures de bruit 1/f ont été comparées aux spécifications ITRS 2013 pour les transistors multi-grilles en vue des futurs nœuds technologiques de la logique CMOS, et démontrent que nos transistors nanofils satisfont les exigences en la matière