Filière technologique hybride InGaAs/SiGe pour applications CMOS

High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe

Strain integration and performance optimization in sub-20nm FDSOI CMOS technology

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO).The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization

2D Steep Transistor Technology: Overcoming Fundamental Barriers in Low-Power Electronics and Ultra-Sensitive Biosensors

In order to sustain the unprecedented growth of the Information Technology, it is necessary to achieve dimensional scalability along with power reduction, which is a daunting challenge. In this dissertation, two-dimensional (2D) materials are explored as promising materials for future electronics since they can, not only enable dimensional scaling without degradation of device electrostatics but it is also shown here, that they are highly potential candidate for interconnects and passive devices. 2D semiconductors are investigated for transistor applications, and novel approach for doping using nanoparticle functionalization is developed. It is also demonstrated that these materials can lead to ideal transfer characteristics. Aimed towards on-chip interconnect and inductor applications, the first detailed methodology for the accurate evaluation of high-frequency impedance of graphene is presented. Using the developed method the intricate high-frequency effects in graphene such as Anomalous Skin Effect (ASE), high-frequency resistance and inductance saturation, intercoupled relation between edge specularity and ASE and the influence of linear dimensions on impedance are investigated in detail for the first time. While 2D materials can address the issue of dimensional scalability, power reduction requires scaling of power supply voltage, which is difficult due to the fundamental thermionic limitation in the steepness of turn-ON characteristics or subthreshold swing (SS) of conventional Field-Effect-Transistors (FETs). To address this issue, a detailed theoretical and experimental analysis of fundamentally different carrier transport mechanism, based on quantum mechanical band-to-band tunneling (BTBT) is presented. This dissertation elucidates an underlying physical concept behind the BTBT process and provides clear insight into the interplay between electron and hole characteristics of carriers within the forbidden gap during tunneling. Moreover, a novel methodology for increasing the BTBT current through incorporation of metallic nanoparticles at the tunnel junction is proposed and theoretically analyzed, followed by experimental demonstration as proof of concept, which can open up new avenues for enhancing the performance of Tunneling-Field-Effect-Transistors (TFETs). This dissertation, also establishes, for the first time, that the material and device technology which have evolved mainly with an aim of sustaining the glorious scaling trend of Information Technology, can also revolutionize a completely diverse field of bio/gas-sensor technology. The unique advantages of 2D semiconductor for electrical sensors is demonstrated and it is shown that they lead to ultra-high sensitivity, and also provide an attractive pathway for single molecular detectability- the holy grail for all biosensing research. Moreover, it is theoretically illustrated that steep turn-ON characteristics, obtained through novel technology such as BTBT, can result in unprecedented performance improvement compared to that of conventional electrical biosensors, with around 4 orders of magnitude higher sensitivity and 10-fold lower detection time. With a view to building ultra-scaled low power electronics as well as highly efficient sensors, new generation of van-der Waal's BTBT junctions combining 2D with 3D materials is proposed and experimentally demonstrated, which not only retain the advantages of 2D films but also leverages the matured doping technology of 3D materials, thus harnessing the best of both worlds. These attributes are instrumental in the achievement of unprecedented BTBT current, which is more than 3 orders of magnitude higher than that of best reported 2D heterojunctions till date. Finally, with the optimization of the novel heterojunctions, this dissertation also achieves a significant milestone, furnishing the first experimental demonstration of TFETs based on 2D channel material to beat the fundamental limitation in subthreshold swing (SS). This device is the first ever TFET, in a planar architecture to achieve sub-thermionic SS over 4 decades of drain current, a necessary characteristic prescribed by the International Technology Roadmap for Semiconductors and in fact, the only TFET to date, to achieve so, in any architecture and in any material platform, at a low power-supply voltage of 0.1 V. It also represents the world's thinnest channel sub-thermionic transistor, thus, cracking the long-standing issue of simultaneous dimensional and power supply scalability and hence, can lead to a paradigm shift in information technology as well as healthcare

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of Inx≥0.53Ga1-xAs/In0.52Al0.48As and Inx≥0.1Ga1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm2/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In0.85Ga0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (Lside) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH4)2S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al2O3/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×1012cm-2eV-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (Id,sat=1.14mA/mm), double peaked transconductance (gm=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (Ron=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of Id,sat (11×), gm (5.5×) and Ron (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (Lside) from 1μm down to 70nm improved Id,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In0.3Ga0.7Sb-channel (Id,sat=49.4mA/mm, gm=12.3mS/mm, Ron=31.7kΩ.μm) and In0.4Ga0.6Sb-channel (Id,sat=38mA/mm, gm=11.9mS/mm, Ron=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS