2,513 research outputs found
Digital PLL for ISM applications
In modern transceivers, a low power PLL is a key block. It is known that with the
evolution of technology, lower power and high performance circuitry is a challenging
demand.
In this thesis, a low power PLL is developed in order not to exceed 2mW of total power
consumption. It is composed by small area blocks which is one of the main demands.
The blocks that compose the PLL are widely abridged and the final solution is shown,
showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with
a frequency range from 400MHz to 1.5GHz, with a 300ÎĽW to approximately 660ÎĽW
power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming
a divide-by-64 divider. The Phase-Detector is a Dual D Flip-Flop detector with a charge
pump. The PLL has less than a 2us lock time and presents a output oscillation of 1GHz,
as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the
specifications.
The main contributions of this thesis are that this PLL can be applied in ISM applications
due to its covering frequency range and low cost 130nm CMOS technology
Phase resetting reveals network dynamics underlying a bacterial cell cycle
Genomic and proteomic methods yield networks of biological regulatory
interactions but do not provide direct insight into how those interactions are
organized into functional modules, or how information flows from one module to
another. In this work we introduce an approach that provides this complementary
information and apply it to the bacterium Caulobacter crescentus, a paradigm
for cell-cycle control. Operationally, we use an inducible promoter to express
the essential transcriptional regulatory gene ctrA in a periodic, pulsed
fashion. This chemical perturbation causes the population of cells to divide
synchronously, and we use the resulting advance or delay of the division times
of single cells to construct a phase resetting curve. We find that delay is
strongly favored over advance. This finding is surprising since it does not
follow from the temporal expression profile of CtrA and, in turn, simulations
of existing network models. We propose a phenomenological model that suggests
that the cell-cycle network comprises two distinct functional modules that
oscillate autonomously and couple in a highly asymmetric fashion. These
features collectively provide a new mechanism for tight temporal control of the
cell cycle in C. crescentus. We discuss how the procedure can serve as the
basis for a general approach for probing network dynamics, which we term
chemical perturbation spectroscopy (CPS)
Hybrid DDS-PLL based reconfigurable oscillators with high spectral purity for cognitive radio
Analytical, design and simulation studies on the performance optimization of reconfigurable architecture of a Hybrid DDS – PLL are presented in this thesis. The original contributions of this thesis are aimed towards the DDS, the dithering (spur suppression) scheme and the PLL. A new design of Taylor series-based DDS that reduces the dynamic power and number of multipliers is a significant contribution of this thesis. This thesis compares dynamic power and SFDR achieved in the design of varieties of DDS such as Quartic, Cubic, Linear and LHSC.
This thesis proposes two novel schemes namely “Hartley Image Suppression” and “Adaptive Sinusoidal Interference Cancellation” overcoming the low noise floor of traditional dithering schemes. The simulation studies on a Taylor series-based DDS reveal an improvement in SFDR from 74 dB to 114 dB by using Least Mean Squares -Sinusoidal Interference Canceller (LM-SIC) with the noise floor maintained at -200 dB.
Analytical formulations have been developed for a second order PLL to relate the phase noise to settling time and Phase Margin (PM) as well as to relate jitter variance and PM. New expressions relating phase noise to PM and lock time to PM are derived. This thesis derives the analytical relationship between the roots of the characteristic equation of a third order PLL and its performance metrics like PM, Gardner’s stability factor, jitter variance, spur gain and ratio of noise power to carrier power. This thesis presents an analysis to relate spur gain and capacitance ratio of a third order PLL. This thesis presents an analytical relationship between the lock time and the roots of its characteristic equation of a third order PLL. Through Vieta’s circle and Vieta’s angle, the performance metrics of a third order PLL are related to the real roots of its characteristic equation
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