Automated Observability Investigation of Analog Electronic Circuits using SPICE

In the present paper, a computer-aided approach to fault observability investigation of linear analog circuits is developed. The method is based on sensitivity investigation of the test characteristics in the frequency domain. The test frequencies are selected maximizing the sensitivity of the magnitude of the test characteristics. Applying postprocessing of the simulation results using macrodefinitions in the graphical analyzer Probe, a fault observability investigation of the circuit is performed. A number of sensitivity measures are defined in Probe for observability investigation of multiple faults using pre-defined macrodefinitions. The sensitivity of S-parameters is obtained in order to investigate the fault observability at RF

Automated Netlist Generation for 3D Electrothermal and Electromagnetic Field Problems

We present a method for the automatic generation of netlists describing general three-dimensional electrothermal and electromagnetic field problems. Using a pair of structured orthogonal grids as spatial discretisation, a one-to-one correspondence between grid objects and circuit elements is obtained by employing the finite integration technique. The resulting circuit can then be solved with any standard available circuit simulator, alleviating the need for the implementation of a custom time integrator. Additionally, the approach straightforwardly allows for field-circuit coupling simulations by appropriately stamping the circuit description of lumped devices. As the computational domain in wave propagation problems must be finite, stamps representing absorbing boundary conditions are developed as well. Representative numerical examples are used to validate the approach. The results obtained by circuit simulation on the generated netlists are compared with appropriate reference solutions.Comment: This is a pre-print of an article published in the Journal of Computational Electronics. The final authenticated version is available online at: https://dx.doi.org/10.1007/s10825-019-01368-6. All numerical results can be reproduced by the Matlab code openly available at https://github.com/tc88/ANTHE

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips

This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, (c) evaluating sensitivity figures, and realize noise and Monte Carlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and improvements.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

Physics-based passivity-preserving parameterized model order reduction for PEEC circuit analysis

The decrease of integrated circuit feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods, and model order reduction (MOR) methods have proven to be very effective in combating such high complexity. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the circuit under study as a function of design parameters such as geometrical and substrate features. Traditional MOR techniques perform order reduction only with respect to frequency, and therefore the computation of a new electromagnetic model and the corresponding reduced model are needed each time a design parameter is modified, reducing the CPU efficiency. Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as geometrical layout or substrate characteristics. We propose a novel PMOR technique applicable to PEEC analysis which is based on a parameterization process of matrices generated by the PEEC method and the projection subspace generated by a passivity-preserving MOR method. The proposed PMOR technique guarantees overall stability and passivity of parameterized reduced order models over a user-defined range of design parameter values. Pertinent numerical examples validate the proposed PMOR approach

Full-Wave Model of Frequency-Dispersive Media With Debye Dispersion Relation by Circuit-Oriented FEM

Dispersive materials play an important role in a wide variety of applications (e.g., waveguides, antenna structures, integrated circuits, bioelectromagnetic applications). In this paper, a full-wave finite-element method (FEM-SPICE) technique for modeling dispersive materials is proposed. A finite-element formulation employing Whitney elements capable of analyzing electromagnetic geometries with dispersive media is described, and a Norton equivalent network is developed for each element. The overall network can be analyzed using a circuit simulator based on SPICE, and is suitable for both frequency- and time-domain analysis. This approach exploits the flexibility of finite-element mesh generation and computational efficiency of modern circuit simulators. Simple test configurations are analyzed to validate the proposed formulation

A nonlinear dynamic S/H-ADC device model based on a modified Volterra series: identification procedure and commercial CAD tool implementation

A nonlinear, dynamic empirical model, based on a Volterra-like approach, was previously proposed by the authors for the time-oriented characterization of sample/hold (S/H) and analog-to-digital conversion (ADC) devices. In this paper, the experimental procedure for model parameter measurement is presented, as well as techniques devoted to the implementation of the model in the framework of the main commercial CAD tools for circuit analysis and design. Examples of simulations, performed both in the time and frequency domain on the model obtained for a commercial device, are proposed, which show the model's capability of pointing out the dynamic nonlinear effects in the S/H-ADC response

Numerical Simulation of Electronic Systems Based on Circuit- Block Partitioning Strategies

Numerical simulation of complex and heterogeneous electronic systems can be a very challenging issue. Circuits composed of a combination of analog, mixed-signal and digital blocks or even radio frequency (RF) blocks, integrated in the same substrate, are very difficult to simulate as a whole at the circuit level. The main reason is because they contain a lot of state variables presenting very distinct properties and evolving in very widely separated time scales. Examples of practical interest are systems-on-a-chip (SoCs), very common in mobile electronics applications, as well as in many other embedded electronic systems. This chapter is intended to briefly review some advanced circuit-level numerical simulation techniques based on circuit-block partitioning schemes, which were especially designed to address the simulation challenges brought by this kind of circuits into the computer-aided-design (CAD) field