Design and Realization of Fully-digital Microwave and Mm-wave Multi-beam Arrays with FPGA/RF-SOC Signal Processing

There has been a constant increase in data-traffic and device-connections in mobile wireless communications, which led the fifth generation (5G) implementations to exploit mm-wave bands at 24/28 GHz. The next-generation wireless access point (6G and beyond) will need to adopt large-scale transceiver arrays with a combination of multi-input-multi-output (MIMO) theory and fully digital multi-beam beamforming. The resulting high gain array factors will overcome the high path losses at mm-wave bands, and the simultaneous multi-beams will exploit the multi-directional channels due to multi-path effects and improve the signal-to-noise ratio. Such access points will be based on electronic systems which heavily depend on the integration of RF electronics with digital signal processing performed in Field programmable gate arrays (FPGA)/ RF-system-on-chip (SoC). This dissertation is directed towards the investigation and realization of fully-digital phased arrays that can produce wideband simultaneous multi-beams with FPGA or RF-SoC digital back-ends. The first proposed approach is a spatial bandpass (SBP) IIR filter-based beamformer, and is based on the concepts of space-time network resonance. A 2.4 GHz, 16-element array receiver, has been built for real-time experimental verification of this approach. The second and third approaches are respectively based on Discrete Fourier Transform (DFT) theory, and a lens plus focal planar array theory. Lens based approach is essentially an analog model of DFT. These two approaches are verified for a 28 GHz 800 MHz mm-wave implementation with RF-SoC as the digital back-end. It has been shown that for all proposed multibeam beamformer implementations, the measured beams are well aligned with those of the simulated. The proposed approaches differ in terms of their architectures, hardware complexity and costs, which will be discussed as this dissertation opens up. This dissertation also presents an application of multi-beam approaches for RF directional sensing applications to explore white spaces within the spatio-temporal spectral regions. A real-time directional sensing system is proposed to capture the white spaces within the 2.4 GHz Wi-Fi band. Further, this dissertation investigates the effect of electro-magnetic (EM) mutual coupling in antenna arrays on the real-time performance of fully-digital transceivers. Different algorithms are proposed to uncouple the mutual coupling in digital domain. The first one is based on finding the MC transfer function from the measured S-parameters of the antenna array and employing it in a Frost FIR filter in the beamforming backend. The second proposed method uses fast algorithms to realize the inverse of mutual coupling matrix via tridiagonal Toeplitz matrices having sparse factors. A 5.8 GHz 32-element array and 1-7 GHz 7-element tightly coupled dipole array (TCDA) have been employed to demonstrate the proof-of-concept of these algorithms

Frequency-Multiplexed Array Digitization for MIMO Receivers: 4-Antennas/ADC at 28 GHz on Xilinx ZCU-1285 RF SoC

Communications at mm-wave frequencies and above rely heavily on beamforming antenna arrays. Typically, hundreds, if not thousands, of independent antenna channels are used to achieve high SNR for throughput and increased capacity. Using a dedicated ADC per antenna receiver is preferable but it\u27s not practical for very large arrays due to unreasonable cost and complexity. Frequency division multiplexing (FDM) is a well-known technique for combining multiple signals into a single wideband channel. In a first of its kind measurements, this paper explores FDM for combining multiple antenna outputs at IF into a single wideband signal that can be sampled and digitized using a high-speed wideband ADC. The sampled signals are sub-band filtered and digitally down-converted to obtain individual antenna channels. A prototype receiver was realized with a uniform linear array consisting of 4 elements with 250 MHz bandwidth per channel at 28 GHz carrier frequency. Each of the receiver chains were frequency-multiplexed at an intermediate frequency of 1 GHz to avoid the requirement for multiple, precise local oscillators (LOs). Combined narrowband receiver outputs were sampled using a single ADC with digital front-end operating on a Xilinx ZCU-1285 RF SoC FPGA to synthesize 4 digital beams. The approach allows $M$ -fold increase in spatial degrees of freedom per ADC, for temporal oversampling by a factor of $M$

Algorithms and Circuits for Analog-Digital Hybrid Multibeam Arrays

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems. In general, N-beam systems using N-element antenna arrays will involve circuit complexities of the order of N2. This dissertation investigates new analog, digital and hybrid low complexity multibeam beamforming algorithms and circuits for reducing the associated high size, weight, and power (SWaP) complexities in larger multibeam arrays. The research efforts on the digital beamforming aspect propose the use of a new class of discrete Fourier transform (DFT) approximations for multibeam generation to eliminate the need for digital multipliers in the beamforming circuitry. For this, 8-, 16- and 32-beam multiplierless multibeam algorithms have been proposed for uniform linear array applications. A 2.4 GHz 16-element array receiver setup and a 5.8 GHz 32-element array receiver system which use field programmable gate arrays (FPGAs) as digital backend have been built for real-time experimental verification of the digital multiplierless algorithms. The multiplierless algorithms have been experimentally verified by digitally measuring beams. It has been shown that the measured beams from the multiplierless algorithms are in good agreement with the exact counterpart algorithms. Analog realizations of the proposed approximate DFT transforms have also been investigated leading to low-complex, high bandwidth circuits in CMOS. Further, a novel approach for reducing the circuit complexity of analog true-time delay (TTD) N-beam beamforming networks using N-element arrays has been proposed for wideband squint-free operation. A sparse factorization of the N-beam delay Vandermonde beamforming matrix is used to reduce the total amount of TTD elements that are needed for obtaining N number of beams in a wideband array. The method has been verified using measured responses of CMOS all-pass filters (APFs). The wideband squint-free multibeam algorithm is also used to propose a new low-complexity hybrid beamforming architecture targeting future 5G mmW systems. Apart from that, the dissertation also explores multibeam beamforming architectures for uniform circular arrays (UCAs). An algorithm having N log N circuit complexity for simultaneous generation of N-beams in an N-element UCA is explored and verified

Embedded Machine Learning: Emphasis on Hardware Accelerators and Approximate Computing for Tactile Data Processing

Machine Learning (ML) a subset of Artificial Intelligence (AI) is driving the industrial and technological revolution of the present and future. We envision a world with smart devices that are able to mimic human behavior (sense, process, and act) and perform tasks that at one time we thought could only be carried out by humans. The vision is to achieve such a level of intelligence with affordable, power-efficient, and fast hardware platforms. However, embedding machine learning algorithms in many application domains such as the internet of things (IoT), prostheses, robotics, and wearable devices is an ongoing challenge. A challenge that is controlled by the computational complexity of ML algorithms, the performance/availability of hardware platforms, and the application\u2019s budget (power constraint, real-time operation, etc.). In this dissertation, we focus on the design and implementation of efficient ML algorithms to handle the aforementioned challenges. First, we apply Approximate Computing Techniques (ACTs) to reduce the computational complexity of ML algorithms. Then, we design custom Hardware Accelerators to improve the performance of the implementation within a specified budget. Finally, a tactile data processing application is adopted for the validation of the proposed exact and approximate embedded machine learning accelerators. The dissertation starts with the introduction of the various ML algorithms used for tactile data processing. These algorithms are assessed in terms of their computational complexity and the available hardware platforms which could be used for implementation. Afterward, a survey on the existing approximate computing techniques and hardware accelerators design methodologies is presented. Based on the findings of the survey, an approach for applying algorithmic-level ACTs on machine learning algorithms is provided. Then three novel hardware accelerators are proposed: (1) k-Nearest Neighbor (kNN) based on a selection-based sorter, (2) Tensorial Support Vector Machine (TSVM) based on Shallow Neural Networks, and (3) Hybrid Precision Binary Convolution Neural Network (BCNN). The three accelerators offer a real-time classification with monumental reductions in the hardware resources and power consumption compared to existing implementations targeting the same tactile data processing application on FPGA. Moreover, the approximate accelerators maintain a high classification accuracy with a loss of at most 5%

Remote Sensing Data Compression

A huge amount of data is acquired nowadays by different remote sensing systems installed on satellites, aircrafts, and UAV. The acquired data then have to be transferred to image processing centres, stored and/or delivered to customers. In restricted scenarios, data compression is strongly desired or necessary. A wide diversity of coding methods can be used, depending on the requirements and their priority. In addition, the types and properties of images differ a lot, thus, practical implementation aspects have to be taken into account. The Special Issue paper collection taken as basis of this book touches on all of the aforementioned items to some degree, giving the reader an opportunity to learn about recent developments and research directions in the field of image compression. In particular, lossless and near-lossless compression of multi- and hyperspectral images still remains current, since such images constitute data arrays that are of extremely large size with rich information that can be retrieved from them for various applications. Another important aspect is the impact of lossless compression on image classification and segmentation, where a reasonable compromise between the characteristics of compression and the final tasks of data processing has to be achieved. The problems of data transition from UAV-based acquisition platforms, as well as the use of FPGA and neural networks, have become very important. Finally, attempts to apply compressive sensing approaches in remote sensing image processing with positive outcomes are observed. We hope that readers will find our book useful and interestin

Recent Advances in Embedded Computing, Intelligence and Applications

The latest proliferation of Internet of Things deployments and edge computing combined with artificial intelligence has led to new exciting application scenarios, where embedded digital devices are essential enablers. Moreover, new powerful and efficient devices are appearing to cope with workloads formerly reserved for the cloud, such as deep learning. These devices allow processing close to where data are generated, avoiding bottlenecks due to communication limitations. The efficient integration of hardware, software and artificial intelligence capabilities deployed in real sensing contexts empowers the edge intelligence paradigm, which will ultimately contribute to the fostering of the offloading processing functionalities to the edge. In this Special Issue, researchers have contributed nine peer-reviewed papers covering a wide range of topics in the area of edge intelligence. Among them are hardware-accelerated implementations of deep neural networks, IoT platforms for extreme edge computing, neuro-evolvable and neuromorphic machine learning, and embedded recommender systems

Digital FPGA Circuits Design for Real-Time Video Processing with Reference to Two Application Scenarios

In the present days of digital revolution, image and/or video processing has become a ubiquitous task: from mobile devices to special environments, the need for a real-time approach is everyday more and more evident. Whatever the reason, either for user experience in recreational or internet-based applications or for safety related timeliness in hard-real-time scenarios, the exploration of technologies and techniques which allow for this requirement to be satisfied is a crucial point. General purpose CPU or GPU software implementations of these applications are quite simple and widespread, but commonly do not allow high performance because of the high layering that separates high level languages and libraries, which enforce complicated procedures and algorithms, from the base architecture of the CPUs that offers only limited and basic (although rapidly executed) arithmetic operations. The most practised approach nowadays is based on the use of Very-Large-Scale Integrated (VLSI) digital electronic circuits. Field Programmable Gate Arrays (FPGAs) are integrated digital circuits designed to be configured after manufacturing, "on the field". They typically provide lower performance levels when compared to Application Specific Integrated Circuits (ASICs), but at a lower cost, especially when dealing with limited production volumes. Of course, on-the-field programmability itself (and re-programmability, in the vast majority of cases) is also a characteristic feature that makes FPGA more suitable for applications with changing specifications where an update of capabilities may be a desirable benefit. Moreover, the time needed to fulfill the design cycle for FPGA-based circuits (including of course testing and debug speed) is much reduced when compared to the design flow and time-to-market of ASICs. In this thesis work, we will see (Chapter 1) some common problems and strategies involved with the use of FPGAs and FPGA-based systems for Real Time Image Processing and Real Time Video Processing (in the following alsoindicated interchangeably with the acronym RTVP); we will then focus, in particular, on two applications. Firstly, Chapter 2 will cover the implementation of a novel algorithm for Visual Search, known as CDVS, which has been recently standardised as part of the MPEG-7 standard. Visual search is an emerging field in mobile applications which is rapidly becoming ubiquitous. However, typically, algorithms for this kind of applications are connected with a high leverage on computational power and complex elaborations: as a consequence, implementation efficiency is a crucial point, and this generally results in the need for custom designed hardware. Chapter 3 will cover the implementation of an algorithm for the compression of hyperspectral images which is bit-true compatible with the CCSDS-123.0 standard algorithm. Hyperspectral images are three dimensional matrices in which each 2D plane represents the image, as captured by the sensor, in a given spectral band: their size may range from several millions of pixels up to billions of pixels. Typical scenarios of use of hyperspectral images include airborne and satellite-borne remote sensing. As a consequence, major concerns are the limitedness of both processing power and communication links bandwidth: thus, a proper compression algorithm, as well as the efficiency of its implementation, is crucial. In both cases we will first of all examine the scope of the work with reference to current state-of-the-art. We will then see the proposed implementations in their main characteristics and, to conclude, we will consider the primary experimental results

Real-Time Narrowband and Wideband Beamforming Techniques for Fully-Digital RF Arrays

Elemental digital beamforming offers increased flexibility for multi-function radio frequency (RF) systems supporting radar and communications applications. As fully digital arrays, components, and subsystems are becoming more affordable in the military and commercial industries, analog components such as phase shifters, filters, and mixers have begun to be replaced by digital circuits which presents efficiency challenges in power constrained scenarios. Furthermore, multi-function radar and communications systems are exploiting the multiple simultaneous beam capability provided by digital at every element beamforming. Along with further increasing data samples rates and increasing instantaneous bandwidths (IBW), real time processing in the digital domain has become a challenge due to the amount of data produced and processed in current systems. These arrays generate hundreds of gigabits per second of data throughput or more which is costly to send off-chip to an adjunct processor fundamentally limiting the overall performance of an RF array system. In this dissertation, digital filtering techniques and architectures are described which calibrate and beamform both narrowband and wideband RF arrays on receive. The techniques are shown to optimize one or many parameters of the digital transceiver system to improve the overall system efficiency. Digitally beamforming in the beamspace is shown to further increase the processing efficiency of an adaptive system compared to state of the art frequency domain approaches by minimizing major processing bottlenecks of generating adaptive filter coefficients. The techniques discussed are compared and contrasted across different hardware processor modules including field-programmable gate arrays (FPGAs), graphical processing units (GPUs), and central processing units (CPUs)

A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi