An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication

An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication

System-on-chip architecture for secure sub-microsecond synchronization systems

213 p.En esta tesis, se pretende abordar los problemas que conlleva la protección cibernética del Precision Time Protocol (PTP). Éste es uno de los protocolos de comunicación más sensibles de entre los considerados por los organismos de estandarización para su aplicación en las futuras Smart Grids o redes eléctricas inteligentes. PTP tiene como misión distribuir una referencia de tiempo desde un dispositivo maestro al resto de dispositivos esclavos, situados dentro de una misma red, de forma muy precisa. El protocolo es altamente vulnerable, ya que introduciendo tan sólo un error de tiempo de un microsegundo, pueden causarse graves problemas en las funciones de protección del equipamiento eléctrico, o incluso detener su funcionamiento. Para ello, se propone una nueva arquitectura System-on-Chip basada en dispositivos reconfigurables, con el objetivo de integrar el protocolo PTP y el conocido estándar de seguridad MACsec para redes Ethernet. La flexibilidad que los modernos dispositivos reconfigurables proporcionan, ha sido aprovechada para el diseño de una arquitectura en la que coexisten procesamiento hardware y software. Los resultados experimentales avalan la viabilidad de utilizar MACsec para proteger la sincronización en entornos industriales, sin degradar la precisión del protocolo

Interoperable data management and instrument control, plug and play concepts and sensor registry experiences at OBSEA

Postprint (published version

Data Acquisition Applications

Data acquisition systems have numerous applications. This book has a total of 13 chapters and is divided into three sections: Industrial applications, Medical applications and Scientific experiments. The chapters are written by experts from around the world, while the targeted audience for this book includes professionals who are designers or researchers in the field of data acquisition systems. Faculty members and graduate students could also benefit from the book

A SECURITY-CENTRIC APPLICATION OF PRECISION TIME PROTOCOL WITHIN ICS/SCADA SYSTEMS

Industrial Control System and Supervisory Control and Data Acquisition (ICS/SCADA) systems are key pieces of larger infrastructure that are responsible for safely operating transportation, industrial operations, and military equipment, among many other applications. ICS/SCADA systems rely on precise timing and clear communication paths between control elements and sensors. Because ICS/SCADA system designs place a premium on timeliness and availability of data, security ended up as an afterthought, stacked on top of existing (insecure) protocols. As precise timing is already resident and inherent in most ICS/SCADA systems, a unique opportunity is presented to leverage existing technology to potentially enhance the security of these systems. This research seeks to evaluate the utility of timing as a mechanism to mitigate certain types of malicious cyber-based operations such as a man-on-the-side (MotS) attack. By building a functioning ICS/SCADA system and communication loop that incorporates precise timing strategies in the reporting and control loop, specifically the precision time protocol (PTP), it was shown that certain kinds of MotS attacks can be mitigated by leveraging precise timing.Navy Cyber Warfare Development Group, Suitland, MDLieutenant, United States NavyApproved for public release. Distribution is unlimited

Collision avoidance for Delay_Req messages in broadcast media

The time accuracy of the Precision Time Protocol deteriorates in consequence to Delay req/Delay resp session collisions common for applications using shared broadcast media. In this paper we propose a protocol that coordinates Delay_req/Delay_resp sessions with minimum changes to the original PTP protocol. Simulations illustrate protocol’s operation and demonstrate significant reduction of session collisions

Simulation and experimental evaluation of a flexible time triggered ethernet architecture applied in satellite nano/micro launchers

The success of small satellites has led to the study of new technologies for the realization of Nano and Micro Launch Vehicle (NMLV) in order to make competitive launch costs. The paper has the objective to define and experimentally investigate the performance of a communication system for NMLV interconnecting the End Systems as On-Board Computer (OBC), telemetry apparatus, Navigation Unit...we propose a low cost Ethernet-based solution able to provide the devices with high interconnection bandwidth. To guarantee hard delays to the Guide, Navigation and Control applications we propose some architectural changes of the traditional Ethernet network with the introduction of a layer implemented in the End Systems and allow for the lack of any contention on the network links. We show how the proposed solution has comparable performance to the one of TTEthernet standard that is a very expensive solution. An experimental test-bed equipped with Ethernet switches and Hercules boards by Texas Instruments is also provided to prove the feasibility of the proposed solution

Sub-Microsecond Time Synchronization for Network-Connected Microcontrollers

This paper presents a bare-metal implementation of the IEEE 1588 Precision Time Protocol (PTP) for network-connected microcontroller edge devices, enabling sub-microsecond time synchronization in automotive networks and multimedia applications. The implementation leverages the hardware timestamping capabilities of the microcontroller (MCU) to implement a two-stage Phase-locked loop (PLL) for offset and drift correction of the hardware clock. Using the MCU platform as a PTP master enables the distribution of a sub-microsecond accurate Global Positioning System (GPS) timing signal over a network. The performance of the system is evaluated using master-slave configurations where the platform is synchronized with a GPS, an embedded platform, and a microcontroller master. Results show that MCU platforms can be synchronized to an external GPS reference over a network with a standard deviation of 40.7 nanoseconds, enabling precise time synchronization for bare-metal microcontroller systems in various applications

Probes of Lorentz Violation in Neutrino Propagation

It has been suggested that the interactions of energetic particles with the foamy structure of space-time thought to be generated by quantum-gravitational (QG) effects might violate Lorentz invariance, so that they do not propagate at a universal speed of light. We consider the limits that may be set on a linear or quadratic violation of Lorentz invariance in the propagation of energetic neutrinos, v/c=[1 +- (E/M_\nuQG1)] or [1 +- (E/M_\nu QG2}^2], using data from supernova explosions and the OPERA long-baseline neutrino experiment. Using the SN1987a neutrino data from the Kamioka II, IMB and Baksan experiments, we set the limits M_\nuQG1 > 2.7(2.5)x10^10 GeV for subluminal (superluminal) propagation, respectively, and M_\nuQG2 >4.6(4.1)x10^4 GeV at the 95% confidence level. A future galactic supernova at a distance of 10 kpc would have sensitivity to M_\nuQG1 > 2(4)x10^11 GeV for subluminal (superluminal) propagation, respectively, and M_\nuQG2 > 2(4)x10^5 GeV. With the current CNGS extraction spill length of 10.5 micro seconds and with standard clock synchronization techniques, the sensitivity of the OPERA experiment would reach M_\nuQG1 ~ 7x10^5 GeV (M_\nuQG2 ~ 8x10^3 GeV) after 5 years of nominal running. If the time structure of the SPS RF bunches within the extracted CNGS spills could be exploited, these figures would be significantly improved to M_\nuQG1 ~ 5x10^7 GeV (M_\nuQG2 ~ 4x10^4 GeV). These results can be improved further if similar time resolution can be achieved with neutrino events occurring in the rock upstream of the OPERA detector: we find potential sensitivities to M_\nuQG1 ~ 4x10^8 GeV and M_\nuQG2 ~ 7x10^5 GeV.Comment: 33 pages, 22 figures, version accepted for publication in Physical Review