Intel 8085 Microprocessor Simulation Tool OneX Simulator

In spite of the advancement in computer architecture and availability of microprocessors (ex. Intel Core i7 etc.) with speed thousand times greater, microprocessor 8085 is still widely used in academia for education and research purposes. To make the microprocessor 8085 more accessible and portable, many simulators for the same have been introduced over the past years with various level of user friendliness. This paper proposes a simple yet powerful enhanced simulator, namely OneX which is capable of real time code parsing, error handling and label parsing for different addresses. Proposed software also addresses few flaws present in the earlier version of 8085 microprocessor software. The latest copy of the software is available at (https://github.com/Pronoy999/Project-OneX

Dynamic partial reconfiguration for pipelined digital systems— A Case study using a color space conversion engine

In digital hardware design, reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) allow for a unique feature called partial reconfiguration PR). This refers to the reprogramming of a subset of the reconfigurable logic during active operation. PR allows multiple hardware blocks to be consolidated into a single partition, which can be reprogrammed at run-time as desired. This may reduce the logic circuit (and silicon area) requirements and greatly extend functionality. Furthermore, dynamic partial reconfiguration (DPR) refers to PR that does not halt the system during reprogramming. This allows for configuration to overlap with normal processing, potentially achieving better system performance than a static(halting) PR implementation. This work has investigated the advantages and trade-offs of DPR as applied to an existing color space conversion(CSC) engine provided by Hewlett-Packard (HP). Two versions were created: a single-pipeline engine, which can only overlap tasks in specific sequences; and a dual-pipeline engine, which can overlap any consecutive tasks. These were implemented in a Virtex-6 FPGA. Data communication occurs over the PCI Express (PCIe) interface. Test results show improvements in execution speed and resource utilization, though some are minor due to intrinsic characteristics of the CSC engine pipeline. The dual-pipeline version outperformed the single-pipeline in most test cases. Therefore, future work will focus on multiple-pipeline architectures

Implementation of soft processor based SOC for JPEG compression on FPGA

With the advent of semiconductor process and EDA tools technology, IC designers can integrate more functions. However, to reduce the demand of time-to-market and tackle the increasing complexity of SoC, the need of fast prototyping and testing is growing. Taking advantage of deep submicron technology, modern FPGAs provide a fast and low-cost prototyping with large logic resources and high performance. So the hardware is mapped onto an emulation platform based on FPGA that mimics the behaviour of SOC. In this paper we use FPGA as a system on chip which is then used for image compression by 2-D DCT respectively and proposed SoC for image compression using soft core Microblaze. The JPEG standard defines compression techniques for image data. As a consequence, it allows to store and transfer image data with considerably reduced demand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process is widely used. Proposed SoC for JPEG compression has been implemented on FPGA Spartan-6 SP605 evaluation board using Xilinx platform studio, because field programmable gate array have reconfigurable hardware architecture. Hence the JPEG image with high speed and reduced size can be obtained at low risk and low power consumption of about 0.699W. The proposed SoC for image compression is evaluated at 83.33MHz on Xilinx Spartan-6 FPGA

A virtual workbench for electric Lego labkits

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.by Jay M. Grabeklis.M.Eng

Precise time dissemination via portable atomic clocks

The most precise operational method of time dissemination over long distances presently available to the Precise Time and Time Interval (PTTI) community of users is by means of portable atomic clocks. The Global Positioning System (GPS), the latest system showing promise of replacing portable clocks for global PTTI dissemination, was evaluated. Although GPS has the technical capability of providing superior world-wide dissemination, the question of present cost and future accessibility may require a continued reliance on portable clocks for a number of years. For these reasons a study of portable clock operations as they are carried out today was made. The portable clock system that was utilized by the U.S. Naval Observatory (NAVOBSY) in the global synchronization of clocks over the past 17 years is described and the concepts on which it is based are explained. Some of its capabilities and limitations are also discussed

"Development of wireless fire products”

The project was to develop a radio controlled door holder system as the first in a range of radio based products for Stephenson Gobin Eng Co. Ltd. Stephenson Gobin manufacture and market a wide range of electromechanical products, including retaining devices for fire doors and smoke vents. Typical installations are in hospitals, nursing homes, shopping centers, hotels or any building open to the public. The author discusses why a radio controlled door holder system is commercially and technically viable. Various wired and Wirefree door holder systems are evaluated on merits of safety and ease of installation. Stephenson Gobin developed a bi-stable latching door holding device which consumed no current in a state that was capable of holding a fire door open. This was due to a rotating magnetic slug assembly which only drew current to latch from one state to other. The device needed to be controlled wirelessly and possible methods of communication were assessed. Communicating using the license free radio frequency spectrum was selected due to the falling costs of radio components and the huge growth in the radio communication sector. The author developed and tested the hardware and software necessary to communicate with and actuate such a device

A rationale and design of a microcomputer system for schools and colleges

Imperial Users onl

A Pilot Program in Internet-of-things with University and Industry Collaboration: Introduction and Lessons Learned

Internet-of-Things (IoT) is one of the most prominent technological eco-systems and an engine of growth with an estimated market size of $14 Trillion to$33 Trillion by 2025 (McKinsey Global Institute). The IoT eco-system uses well-established technologies in many fields; and it adds new and often challenging requirements on extant techniques. For example, many wireless schemes are or being redesigned to address battery life and cost of solution issues. At the same time, the industry needs to hire and retrain many technical personnel to address these issues and support this newly evolving eco-system in many different markets. These facts culminate in the need for engineering students to be skilled to handle the new challenges and match the hiring market needs. As importantly, the more experienced technical personnel need to be retrained to understand this evolving eco-system. In this light, we have taken parallel symbiotic steps to address these challenges. We have piloted a course in IoT covering the most critical technologies in a typical end-to-end IoT system, including various access technologies and higher layer protocols and standards as well as prominent cloud services. Our industry partner has developed new measurement equipment to address more accurate and sensitive current draw of circuits to assist with power-frugal designs for long battery life. They have also developed a programmable board along with several experiments geared towards IoT applications. Last summer a small group of graduate students, with the guidance of a senior faculty member, used the IoT board to assess its efficacy for less experienced engineering students. The board and the associated experiments were found to be very useful and a good addition to the program. The experiments are also valuable for continuing education purposes for developing specific skills in the development of IoT systems. The team created an updated and tailored user’s manual to better serve the needs of less experienced engineering students and to alleviate the initial frustration associated with setting up the system. In this paper, we will present the experiences of the pilot program and the key points that present the enhancements of technical manual for a teaching environment. We will present the value that the IoT board and its experiments bring to the students in order to enhance their experience when learning about the IoT eco-system

Empirical and Statistical Application Modeling Using on -Chip Performance Monitors.

To analyze the performance of applications and architectures, both programmers and architects desire formal methods to explain anomalous behavior. To this end, we present various methods that utilize non-intrusive, performance-monitoring hardware only recently available on microprocessors to provide further explanations of observed behavior. All the methods attempt to characterize and explain the instruction-level parallelism achieved by codes on different architectures. We also present a prototype tool automating the analysis process to exploit the advantages of the empirical and statistical methods proposed. The empirical, statistical and hybrid methods are discussed and explained with case study results provided. The given methods further the wealth of tools available to programmer\u27s and architects for generally understanding the performance of scientific applications. Specifically, the models and tools presented provide new methods for evaluating and categorizing application performance. The empirical memory model serves to quantify the hierarchical memory performance of applications by inferring the incurred latencies of codes after the effect of latency hiding techniques are realized. The instruction-level model and its extensions model on-chip performance analytically giving insight into inherent performance bottlenecks in superscalar architectures. The statistical model and its hybrid extension provide other methods of categorizing codes via their statistical variations. The PTERA performance tool automates the use of performance counters for use by these methods across platforms making the modeling process easier still. These unique methods provide alternatives to performance modeling and categorizing not available previously in an attempt to utilize the inherent modeling capabilities of performance monitors on commodity processors for scientific applications