Soft error in FPGA-implemented asynchronous circuits

In this paper, we investigate the mechanism of soft error generation and propagation in asynchronous circuits which are implemented on FPGAs. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed. The results show that it is much easier to detect the soft error in asynchronous circuits implemented on FPGAs so that FPGAs can be reprogrammed, compared with traditional synchronous circuits

A soft error mitigation scheme to increase the resilience of register file

Abstract Register files are essential and integral part of any microprocessor architecture. Soft errors in the register file can quickly spread to various parts of the system and result in silent data corruption. Traditional redundancy based schemes to protect the register file are prohibitive because register file is often in the timing critical path of the processor. Since it is one of the hottest blocks on the chip, adding any extra circuitry to it is not desirable. For embedded systems under severe cost constraints, where power, performance, area and reliability cannot be simply compromised, we propose a soft error reduction technique for register files. This thesis introduces a soft error mitigation scheme, called Self-Immunity to increase the resilience of the register file from soft errors, by using unused bits of the register file. It is desirable for processors that demand high register file integrity under stringent constraints. This thesis explains the implementation of our proposed technique to protect the register file from soft errors. And show the best overall results compared to state-of-the-art in register file vulnerability reduction with minimum impact on the area and power

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling soft errors in the logic and memories that allow meeting the desired failures-in-time (FIT) target are key to keep harnessing the benefits of Moore's law. The failure to scale the soft error rate caused by particle strikes, may soon limit the total number of cores that one may have running at the same time. This paper proposes a light-weight and scalable architecture to eliminate silent data corruption errors (SDC) and detected unrecoverable errors (DUE) of a core. The architecture uses acoustic wave detectors for error detection. We propose to recover by confining the errors in the cache hierarchy, allowing us to deal with the relatively long detection latencies. Our results show that the proposed mechanism protects the whole core (logic, latches and memory arrays) incurring performance overhead as low as 0.60%. © 2014 IEEE.Peer ReviewedPostprint (author's final draft

A Joint PHY/MAC Architecture for Low-Radiated Power TH-UWB Wireless Ad-Hoc Networks

Due to environmental concerns and strict constraints on interference imposed on other networks, the radiated power of emerging pervasive wireless networks needs to be strictly limited, yet without sacrificing acceptable data rates. Pulsed Time-Hopping Ultra-Wide Band (TH-UWB) is a radio technology that has the potential to satisfy this requirement. Although TH-UWB is a multi-user radio technology, non-zero cross-correlation between time-hopping sequences, time-asynchronicity between sources and a multipath channel environment make it sensitive to strong interferers and near-far scenarios. While most protocols manage interference and multiple-access through power control or mutual exclusion (CSMA/CA or TDMA), we base our design on rate control, a relatively unexplored dimension for multiple-access and interference management. We further take advantage of the nature of pulsed TH-UWB to propose an interference mitigation scheme that reduces the impact of strong interferers. A source is always allowed to send and continuously adapts its channel code (hence its rate) to the interference experienced at the destination. In contrast to power control or exclusion, our MAC layer is local to sender and receiver and does not need coordination among neighbors not involved in the transmission. We show by simulation that we achieve a significant increase in network throughput

Design for soft error tolerance in FPGA-implemented asynchronous circuits

This research in its present form is the result of experimentation on effect of soft error in FPGA-implemented asynchronous circuit. The conclusion are drawn that asynchronous circuit are much easier to detect soft error than synchronous circuits. The asynchronous circuit is implemented in FPGA with software fault injection method to analyze the behavior of soft error generation in FPGA implementation asynchronous circuits. The proposed detection circuit can detect all soft errors that generated in FPGA-implemented asynchronous circuit. The contributions include: investigation of FPGA structure, investigation of soft error model in FPGA, mechanism of FPGA implemented asynchronous circuit, behavior of soft error injection in FPGA look up table that implemented asynchronous circuit, and proposed detection scheme. The research on soft error injection in FPGA routing system and soft error rate estimation will be done in the future

Asynchronous CDMA Systems with Random Spreading-Part I: Fundamental Limits

Spectral efficiency for asynchronous code division multiple access (CDMA) with random spreading is calculated in the large system limit allowing for arbitrary chip waveforms and frequency-flat fading. Signal to interference and noise ratios (SINRs) for suboptimal receivers, such as the linear minimum mean square error (MMSE) detectors, are derived. The approach is general and optionally allows even for statistics obtained by under-sampling the received signal. All performance measures are given as a function of the chip waveform and the delay distribution of the users in the large system limit. It turns out that synchronizing users on a chip level impairs performance for all chip waveforms with bandwidth greater than the Nyquist bandwidth, e.g., positive roll-off factors. For example, with the pulse shaping demanded in the UMTS standard, user synchronization reduces spectral efficiency up to 12% at 10 dB normalized signal-to-noise ratio. The benefits of asynchronism stem from the finding that the excess bandwidth of chip waveforms actually spans additional dimensions in signal space, if the users are de-synchronized on the chip-level. The analysis of linear MMSE detectors shows that the limiting interference effects can be decoupled both in the user domain and in the frequency domain such that the concept of the effective interference spectral density arises. This generalizes and refines Tse and Hanly's concept of effective interference. In Part II, the analysis is extended to any linear detector that admits a representation as multistage detector and guidelines for the design of low complexity multistage detectors with universal weights are provided

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicron CMOS Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented