Integration of magnetic amplifier switch model into computer aided design for power converters

Зазвичай у джерелах вторинного електроживлення (ДВЕЖ) комутаційну та регулюючу функції виконують напівпровідникові компоненти. Однак вони не можуть забезпечити високу якість вихідних характеристик у багатоканальних джерелах живлення та в ДВЕЖ із високим рівнем струму навантаження. В таких випадках як силові ключі використовують високочастотні магнітні підсилювачі (ВМП) на основі аморфних магнітом’яких сплавів з прямокутною петлею гістерезису. Розроблення перетворювачів електроенергії на основі ВМП не є повністю автоматизованим. ВМП є магнітним компонентом з нелінійними властивостями. Системи автоматизованого проектування (САПР) для комп’ютерного імітаційного моделювання електричних кіл не призначені для розрахунків магнітних полів та працюють з дискретними електричними компонентами. Існує проблема інтеграції моделі компонента з магнітним гістерезисом у бібліотеку моделей САПР. Крім того, досить складно оцінити оптимальні параметри такого компонента. У статті запропоновано нову математичну модель силового ключа на основі ВМП, що ґрунтується на функції, яку можна генерувати з допомогою цифрових технологій. Досліджено цифровий генератор синуса, що складається з цифрових дискретних компнентів для моделювання силового ключа на основі ВМП. Запропоновану математичну модель силового ключа на основі ВМП інтегровано у САПР. Проведено комп’ютерне імітаційне моделювання електричного кола, що містить ВМП. Розраховано абсолютну похибку та середньоквадратичне відхилення моделі процесів перемагнічення ВМП у порівнянні з експериментально отриманими даними. Така часткова автоматизація процесу розроблення високочастотних перетворювачів електроенергії на основі ВМП суттєво зменшить його складність, тривалість і вартість, а також сприятиме розвиткові нових схемотехнічних рішень.The designing of electrical power converters based on Magnetic Amplifier (MagAmp) switches is not fully automated. MagAmp is a magnetic component with nonlinear properties. Computer aided design (CAD) programmes are built to simulate electric circuits without electromagnetic field with distributed components. There is a problem of integration of a model of a component with magnetic hysteresis into the set of CAD models. In addition, estimation of the optimal parameters of such a component is rather complicated. The article proposes a new model of MagAmp switch which is based on a function that can be generated using digital technology. The digital generator of sinusoidal signals, consisting of discrete digital components for modeling the MagAmp switch, is investigated. Integration of the model into CAD programme and simulation of the electric circuit, which includes MagAmp switch, are obtained. Partial automation will reduce complexity, duration and cost of the design procedure, and will enhance the development of power converters

Modeling and Analysis of Power Processing Systems

The feasibility of formulating a methodology for the modeling and analysis of aerospace electrical power processing systems is investigated. It is shown that a digital computer may be used in an interactive mode for the design, modeling, analysis, and comparison of power processing systems

ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

The Expanded Very Large Array

In almost 30 years of operation, the Very Large Array (VLA) has proved to be a remarkably flexible and productive radio telescope. However, the basic capabilities of the VLA have changed little since it was designed. A major expansion utilizing modern technology is currently underway to improve the capabilities of the VLA by at least an order of magnitude in both sensitivity and in frequency coverage. The primary elements of the Expanded Very Large Array (EVLA) project include new or upgraded receivers for continuous frequency coverage from 1 to 50 GHz, new local oscillator, intermediate frequency, and wide bandwidth data transmission systems to carry signals with 16 GHz total bandwidth from each antenna, and a new digital correlator with the capability to process this bandwidth with an unprecedented number of frequency channels for an imaging array. Also included are a new monitor and control system and new software that will provide telescope ease of use. Scheduled for completion in 2012, the EVLA will provide the world research community with a flexible, powerful, general-purpose telescope to address current and future astronomical issues.Comment: Added journal reference: published in Proceedings of the IEEE, Special Issue on Advances in Radio Astronomy, August 2009, vol. 97, No. 8, 1448-1462 Six figures, one tabl

SIMPLIS efficiency model for a synchronous multiphase buck converter

In this master’s thesis, an efficiency model was developed for the synchronous multiphase buck converters of the TPS6594x-Q1 integrated circuit using SIMPLIS simulator. The model includes internal losses occurring in power stage transistors, power stage drivers and bondwires. Modeled external losses include printed circuit board resistance and inductance, inductor direct and alternating current characteristics as well as capacitor nonidealities. Internal loss modeling was mostly based on Cadence simulations. Power stage transistors especially were thoroughly modeled. The capacitances of the power stage transistors were extracted by integrating gate and drain currents during the transistor on and off transitions. Charging of the parasitic capacitances followed the theory in turn-off and turn-on transitions and therefore the capacitance extraction was fairly simple. Nonlinearities of the parasitic capacitors were modeled in SIMPLIS with multiple linear approximations. Transistor gate drivers were very rough approximations of the real drivers but good enough for the simulation model. Drivers were modeled to match the gate currents simulated in Cadence, which were then combined the accurate switching transistor models in order to accurately model the switching characteristics. External loss models were based on measurements and simulations. Printed circuit board losses were based on Ansys simulations in which the printed circuit board inductances and resistances were solved from the geometry of the printed circuit board. Inductors were modeled to match the datasheet impedance and resistance graphs and the model was verified against the measurements done in the laboratory. An automated measurement testbench was done for the inductor measurements using LabVIEW and the results were parsed using Matlab. A ladder topology with resistances and inductances was used in the final inductor model to model the frequency characteristics of the inductor. The effect of direct current on inductance was also investigated but the inductance reduction did not have any significant impact on efficiency. Other external components such as capacitors also cause some external losses and they were modeled based on the capacitor datasheets. The simulation model was compared against single- and two-phase efficiency measurements with multiple different input and output voltages which were chosen to match the most common use cases. Efficiency curves were drawn for each configuration using the implemented simulation model and over 300 different comparison points were compared in total. A post processing script that was launched after a simulation completes had to be written with the programming language SIMPLIS supports to draw the efficiency graph from the simulated data. Using the script allowed to run the efficiency simulation without any additional licenses other than the SIMPLIS license. The final model achieved an average error of under 1 % between all the measured and simulated efficiency curves. The most accurate results were obtained with lower switching frequency and larger inductance. Apart from accuracy, the simulator had to be practical and therefore the simulation time had to be considered. Simulation time was attempted to be kept at minimum by simplifying the schematic in as many ways as possible without losing accuracy. For example, reducing the point of the linear approximations in the power stage transistors from 79 points to 17 points saved nearly 50 seconds in single-phase simulations without significant changes in simulation accuracy

Single-Chip Isolated DC-DC Converter with Self-Tuned Maximum Power Transfer Frequency

abstract: There is an increasing demand for fully integrated point-of-load (POL) isolated DC-DC converters that can provide an isolation barrier between the primary and the secondary side, while delivering a low ripple, low noise regulated voltage at their isolated sides to a high dynamic range, sensitive mixed signal devices, such as sensors, current-shunt-monitors and ADCs. For these applications, smaller system size and integration level is important because the whole system may need to fit to limited space. Traditional methods for providing isolated power are discrete solutions using bulky transformers. Miniaturization of isolated POL regulators is becoming highly desirable for low power applications. A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A Hybrid Method of Performing Electric Power System Fault Ride-Through Evaluations on Medium Voltage Multi-Megawatt Devices

This dissertation explores the design and analysis of a Hybrid Method of performing electrical power system fault ride-through evaluations on multi-megawatt, medium voltage power conversion equipment. Fault ride-through evaluations on such equipment are needed in order to verify and validate full scale designs prior to being implemented in the field. Ultimately, these evaluations will help in reducing the deployment risks associated with bringing new technologies into the marketplace. This is especially true for renewable energy and utility scale energy storage systems, where a significant amount of attention in recent years has focused on their ever increasing role in power system security and stability. The Hybrid Method couples two existing technologies together - a reactive voltage divider network and a power electronic variable voltage source - in order to overcome the inherent limitation of both methods, namely the short circuit duty required for implementation. This work provides the background of this limitation with respect to the existing technologies and demonstrates that the Hybrid Method can minimize the fault duty required for fault evaluations. The physical system, control objectives, and operation cycle of the Hybrid Method are analyzed with respect to the overall objective of reducing the fault duty of the system. A vector controller is designed to incorporate the time variant nature of the Hybrid Method operation cycle, limit the fault current seen by the power electronic variable voltage source, and provide regulation of the voltage at the point of common coupling with the device being evaluated. In order to verify the operation of both the Hybrid Method physical system and vector controller, a controller hardware-in-the-loop experiment is created in order to simulate the physical system in real-time against the prototype implementation of the vector controller. The physical system is simulated in a Real Time Digital Simulator and is controlled with the Hybrid Method vector controller implemented on a National Instruments FPGA. In order to evaluate the complete performance of the Hybrid Method, both a synchronous generator and a doubly-fed induction generator are modeled as the device under test in the simulations of the physical system. Finally, the results of the controller hardware-in-the-loop experiments are presented which demonstrate that the Hybrid Method is a viable solution to performing fault ride-through evaluations on multi-megawatt, medium voltage power conversion equipment