Generating Test Sequences and Slices for Simulink/Stateflow Models

In a typical software development project more than 50 percent of software development effort is spent in testing phase. Test case design as well as execution consumes a lot of time. So automated generation of test cases is highly required. In our thesis we generated test sequences from Simulink/Stateflow, which is used to develop Embedded control systems. Testing of these systems is very important in order to provide error free systems as well as quality assurance. For these purpose Test cases are used to test the systems. We developed the test sequences which are use to generate test cases. First, we represent the System using Simulink/Stateflow models. For this purpose normally we use Simulink tool, which is available in the MATLAB. We developed the dependency graph from the SL/SF model. For Simulink part of the model we use Out put dependency and for the Stateflow part of the model we use Control dependency graph. From those graphs we generate the test sequences. Simulink/Stateflow models often consist of more than ten thousand blocks and a large number of hierarchi-cal levels. In this, we present an approach for slicing Simulink/Stateflow models using dependence graphs from the automotive and avionics do-main. With slicing, the complexity of a model can be reduced to a given point of interest by removing unrelated model elements

Incremental bounded model checking for embedded software

Program analysis is on the brink of mainstream usage in embedded systems development. Formal verification of behavioural requirements, finding runtime errors and test case generation are some of the most common applications of automated verification tools based on bounded model checking (BMC). Existing industrial tools for embedded software use an off-the-shelf bounded model checker and apply it iteratively to verify the program with an increasing number of unwindings. This approach unnecessarily wastes time repeating work that has already been done and fails to exploit the power of incremental SAT solving. This article reports on the extension of the software model checker CBMC to support incremental BMC and its successful integration with the industrial embedded software verification tool BTC EMBEDDED TESTER. We present an extensive evaluation over large industrial embedded programs, mainly from the automotive industry. We show that incremental BMC cuts runtimes by one order of magnitude in comparison to the standard non-incremental approach, enabling the application of formal verification to large and complex embedded software. We furthermore report promising results on analysing programs with arbitrary loop structure using incremental BMC, demonstrating its applicability and potential to verify general software beyond the embedded domain

Program Semantics in Model-Based WCET Analysis: A State of the Art Perspective

Advanced design techniques of safety-critical applications use specialized development model based methods. Under this setting, the application exists at several levels of description, as the result of a sequence of transformations. On the positive side, the application is developed in a systematic way, while on the negative side, its high-level semantics may be obfuscated when represented at the lower levels. The application should provide certain functional and non-functional guarantees. When the application is a hard real-time program, such guarantees could be deadlines, thus making the computation of worst-case execution time (WCET) bounds mandatory. This paper overviews, in the context of WCET analysis, what are the existing techniques to extract, express and exploit the program semantics along the model-based development workflow

Replicability Study: Corpora For Understanding Simulink Models & Projects

Background: Empirical studies on widely used model-based development tools such as MATLAB/Simulink are limited despite the tools' importance in various industries. Aims: The aim of this paper is to investigate the reproducibility of previous empirical studies that used Simulink model corpora and to evaluate the generalizability of their results to a newer and larger corpus, including a comparison with proprietary models. Method: The study reviews methodologies and data sources employed in prior Simulink model studies and replicates the previous analysis using SLNET. In addition, we propose a heuristic for determining code-generating Simulink models and assess the open-source models' similarity to proprietary models. Results: Our analysis of SLNET confirms and contradicts earlier findings and highlights its potential as a valuable resource for model-based development research. We found that open-source Simulink models follow good modeling practices and contain models comparable in size and properties to proprietary models. We also collected and distribute 208 git repositories with over 9k commits, facilitating studies on model evolution. Conclusions: The replication study offers actionable insights and lessons learned from the reproduction process, including valuable information on the generalizability of research findings based on earlier open-source corpora to the newer and larger SLNET corpus. The study sheds light on noteworthy attributes of SLNET, which is self-contained and redistributable

Generalized observational slicing for tree-represented modelling languages

Model-driven software engineering raises the abstraction level making complex systems easier to understand than if written in textual code. Nevertheless, large complicated software systems can have large models, motivating the need for slicing techniques that reduce the size of a model. We present a generalization of observation-based slicing that allows the criterion to be defined using a variety of kinds of observable behavior and does not require any complex dependence analysis. We apply our implementation of generalized observational slicing for tree-structured representations to Simulink models. The resulting slice might be the subset of the original model responsible for an observed failure or simply the sub-model semantically related to a classic slicing criterion. Unlike its predecessors, the algorithm is also capable of slicing embedded Stateflow state machines. A study of nine real-world models drawn from four different application domains demonstrates the effectiveness of our approach at dramatically reducing Simulink model sizes for realistic observation scenarios: for 9 out of 20 cases, the resulting model has fewer than 25% of the original model's elements

Finding Dependency, Test Sequences and Test Cases for Simulink/Stateflow Models

The Simulink/Stateflow (SL/SF) acquiring from Mathworks is fitting the de facto standard in industry for model based development especially for embedded control systems. Many industrial tools are available in the market for test case generation from SL/SF designs; though, we have observed that these tools do not accomplish satisfactory coverage in cases when designs involve non-linear blocks and Stateflow blocks transpire deeper inside the Simulink blocks. For this purpose, we have proposed a methodology that generates the test sequences and test cases from the Simulink/Stateflow model. In our approach, first, we have developed a SL/SF model using MATLAB tool which generates mdl(model description language) file. Next, we convert that mdl file into xml file and then the xml file and mdl file path are passed as an inputs to our proposed methodology to generate Simulink/Stateflow dependency graph(SSDG); Now using the SSDG, we generate test sequences by applying depth first search approach(DFS). Next, for each test sequence, we generate a set of test cases and finally we prioritize those test cases using information flow(IF)value. Sl/SF model allows modelling the systems, simulating and analyzing dynamic systems. The resultant Simulink/Stateflow models consist of large numbers of blocks and states likes more than ten thousand blocks. Hence, to certify the quality of such control system models, automated static analyses and slicing methods are necessary to deal with this complexity. Hence, these approaches help in debugging the model, understanding the behavior of models,identifying faults,if occurs. In this thesis, we present an approach for computing intra-dependencies between blocks by the concept of slicing approach and we represent the result using dependence graphs. With the help of slicing approach, the complexity of a system model can be compact to a specified point of interest(Slicing Criterion) concern by removing unrelated blocks in model system

Power Electronics Controller Prototyping Tool For Power System Applications

Many types of devices based on power converters have been proposed and studied for utility applications. In recent years most of the control systems for these converters have been digital. Unfortunately, such digital controllers, which are often based on a digital signal processor (DSP), are difficult to model in simulation. Thus, hardware prototypes are usually required. This thesis presents a tool for fast prototyping that helps overcome these difficulties. Namely, a hardware-in-the-loop simulation is provided for the digital controller in order to evaluate control algorithms without the voltage source converter and power system. The controller in the loop design methodology is described and the division between the real-time power system model and the hardware controller with an interface is shown. Also, the modulation type, integration time step selection and synchronization between the controller and the real-time system simulation are discussed. The hardware configuration for the real-time simulator and the software implementation of the simulator is discussed. In this thesis an example application of a shunt active compensator following this formal procedure is presented. The active compensator prototyping was first developed in MATLAB/Simulink. Then, following a formal design procedure, the power system was modeled in a digital simulator and the controller was implemented in a digital controller board. Finally, a hardware-in-the-loop test was carried out to validate the performance of the hardware controller for the active compensator. Although the tools and methods presented here are aimed at shunt connected current controller application, they may be generalized for use in the development of any digitally controlled power electronic converter

Generation and prioritization of test casesusing Simulink/Stateflow models

Embedded systems are mainly modeled by using MATLAB's simulink and stateflow tools. MATLAB's simulink is a tool for modeling, simulating and analysing software systems and stateflow is a control logic tool used to model event-driven systems (Reactive systems) through state machines and flow charts within a simulink model. In real-time, systems undergo frequent changes, thus complexity of the systems grows and testing of the systems become time consuming and expensive even if changes occur in small parts of the system. So, these models need formal verification. In this paper, we focus on event-driven systems which are captured by stateflow model. For this, we propose an algorithm (\textit{GenerateGraph}) in which we first generate an XML file for the stateflow model of a system. Then, we parse that XML file following top-down approach by using XML parser. Next, we generate intermediate graph for the model, using the parsed information. By using this graph, we generate test cases for the models of the systems having composite states