Taming Reversible Halftoning via Predictive Luminance

Traditional halftoning usually drops colors when dithering images with binary dots, which makes it difficult to recover the original color information. We proposed a novel halftoning technique that converts a color image into a binary halftone with full restorability to its original version. Our novel base halftoning technique consists of two convolutional neural networks (CNNs) to produce the reversible halftone patterns, and a noise incentive block (NIB) to mitigate the flatness degradation issue of CNNs. Furthermore, to tackle the conflicts between the blue-noise quality and restoration accuracy in our novel base method, we proposed a predictor-embedded approach to offload predictable information from the network, which in our case is the luminance information resembling from the halftone pattern. Such an approach allows the network to gain more flexibility to produce halftones with better blue-noise quality without compromising the restoration quality. Detailed studies on the multiple-stage training method and loss weightings have been conducted. We have compared our predictor-embedded method and our novel method regarding spectrum analysis on halftone, halftone accuracy, restoration accuracy, and the data embedding studies. Our entropy evaluation evidences our halftone contains less encoding information than our novel base method. The experiments show our predictor-embedded method gains more flexibility to improve the blue-noise quality of halftones and maintains a comparable restoration quality with a higher tolerance for disturbances.Comment: to be published in IEEE Transactions on Visualization and Computer Graphic

Wavelet techniques for reversible data embedding into images

The proliferation of digital information in our society has enticed a lot of research into data embedding techniques that add information to digital content like images, audio and video. This additional information can be used for various purposes and different applications place different requirements on the embedding techniques. In this paper, we investigate high capacity lossless data embedding methods that allow one to embed large amounts of data into digital images (or video) in such a way that the original image can be reconstructed from the watermarked image. The paper starts by briefly reviewing three existing lossless data embedding techniques as described by Fridrich and co-authors, by Tian, and by Celik and co-workers. We then present two new techniques: one based on least significant bit prediction and Sweldens' lifting scheme and another that is an improvement of Tian's technique of difference expansion. The various embedding methods are then compared in terms of capacity-distortion behaviour, embedding speed, and capacity control

On the number of rectangulations of a planar point set

AbstractWe investigate the number of different ways in which a rectangle containing a set of n noncorectilinear points can be partitioned into smaller rectangles by n (nonintersecting) segments, such that every point lies on a segment. We show that when the relative order of the points forms a separable permutation, the number of rectangulations is exactly the (n+1)st Baxter number. We also show that no matter what the order of the points is, the number of guillotine rectangulations is always the nth Schröder number, and the total number of rectangulations is O(20n/n4)

Reversible Computation: Extending Horizons of Computing

This open access State-of-the-Art Survey presents the main recent scientific outcomes in the area of reversible computation, focusing on those that have emerged during COST Action IC1405 "Reversible Computation - Extending Horizons of Computing", a European research network that operated from May 2015 to April 2019. Reversible computation is a new paradigm that extends the traditional forwards-only mode of computation with the ability to execute in reverse, so that computation can run backwards as easily and naturally as forwards. It aims to deliver novel computing devices and software, and to enhance existing systems by equipping them with reversibility. There are many potential applications of reversible computation, including languages and software tools for reliable and recovery-oriented distributed systems and revolutionary reversible logic gates and circuits, but they can only be realized and have lasting effect if conceptual and firm theoretical foundations are established first

Introduction to Transformers: an NLP Perspective

Transformers have dominated empirical machine learning models of natural language processing. In this paper, we introduce basic concepts of Transformers and present key techniques that form the recent advances of these models. This includes a description of the standard Transformer architecture, a series of model refinements, and common applications. Given that Transformers and related deep learning techniques might be evolving in ways we have never seen, we cannot dive into all the model details or cover all the technical areas. Instead, we focus on just those concepts that are helpful for gaining a good understanding of Transformers and their variants. We also summarize the key ideas that impact this field, thereby yielding some insights into the strengths and limitations of these models.Comment: 119 pages and 21 figure

Reversible Computation: Extending Horizons of Computing

This open access State-of-the-Art Survey presents the main recent scientific outcomes in the area of reversible computation, focusing on those that have emerged during COST Action IC1405 "Reversible Computation - Extending Horizons of Computing", a European research network that operated from May 2015 to April 2019. Reversible computation is a new paradigm that extends the traditional forwards-only mode of computation with the ability to execute in reverse, so that computation can run backwards as easily and naturally as forwards. It aims to deliver novel computing devices and software, and to enhance existing systems by equipping them with reversibility. There are many potential applications of reversible computation, including languages and software tools for reliable and recovery-oriented distributed systems and revolutionary reversible logic gates and circuits, but they can only be realized and have lasting effect if conceptual and firm theoretical foundations are established first

Scalable diversified antirandom test pattern generation with improved fault coverage for black-box circuit testing

Pseudorandom testing is incapable of utilizing the success rate of preceding test patterns while generating subsequent test patterns. Many redundant test patterns have been generated that increase the test length without any significant increase in the fault coverage. An extension to pseudorandom testing is Antirandom that induces divergent patterns by maximizing the Total Hamming Distance (THD) and Total Cartesian Distance (TCD) of every subsequent test pattern. However, the Antirandom test sequence generation algorithm is prone to unsystematic selection when more than one patterns possess maximum THD and TCD. As a result, diversity among test sequences is compromised, lowering the fault coverage. Therefore, this thesis analyses the effect of Hamming distance in vertical as well as horizontal dimension to enhance diversity among test patterns. First contribution of this thesis is the proposal of a Diverse Antirandom (DAR) test pattern generation algorithm. DAR employs Horizontal Total Hamming Distance (HTHD) along with THD and TCD for diversity enhancement among test patterns as maximum distance test pattern generation. The HTHD and TCD are used as distance metrics that increase computational complexity in divergent test sequence generation. Therefore, the second contribution of this thesis is the proposal of tree traversal search method to maximize diversity among test patterns. The proposed method uses bits mutation of a temporary test pattern following a path leading towards maximization of TCD. Results of fault simulations on benchmark circuits have shown that DAR significantly improves the fault coverage up to 18.3% as compared to Antirandom. Moreover, the computational complexity of Antirandom is reduced from exponential O(2n) to linear O(n). Next, the DARalgorithm is modified to ease hardware implementation for on-chip test generation. Therefore, the third contribution of this thesis is the design of a hardware-oriented DAR (HODA) test pattern generator architecture as an alternative to linear feedback shift register (LFSR) that consists of large number of memory elements. Parallel concatenation of the HODA architecture is designed to reduce the number of memory elements by implementing bit slicing architecture. It has been proven through simulation that the proposed architecture has increased fault coverage up to 66% and a reduction of 46.59% gate count compared to the LFSR. Consequently, this thesis presents uniform and scalable test pattern generator architecture for built-in self-test (BIST) applications and solution to maximum distance test pattern generation for high fault coverage in black-box environment

A Synthetic Circuit For Control Of The Bacterial Dna Damage Response Without Dna Damage

Prokaryotes possess a remarkable ability to respond to environmental stressors using simple genetic circuits that detect signals of stress and mount an appropriate response. The SOS pathway is an example of such a genetic circuit mediating error-prone DNA repair in response to DNA damage. Native control over the SOS pathway is orchestrated by the repressor-protease, LexA. Following a DNA damaging event, the damage sensor RecA activates LexA to undergo a self-cleavage reaction that results in LexA dissociation from SOS promoters and subsequent pathway activation. However, the inability to decouple upstream events – DNA damage and RecA activation – from LexA cleavage by genetic means alone has limited our ability to wholly understand how the SOS pathway contributes to repair, mutagenesis, and bacterial survival. We sought to overcome this limitation by designing a synthetic circuit to orthogonally control SOS activation independent of native signals. Chapter 2 describes the design of the synthetic circuit, in which an exogenously cleavable LexA variant was engineered by embedding a recognition site for TEV protease into the LexA flexible linker region. TEV expression was placed under the control of the small-molecule anhydrotetracycline (ATc), decoupling LexA cleavage from DNA damage and RecA. We show that addition of ATc to strains harboring our synthetic circuit permits small-molecule inducible UV resistance and inducible mutagenesis. Further, exploiting our ability to activate SOS genes independently of upstream events, we show that SOS pathway activation alone is insufficient for mutagenesis, but instead demonstrate the importance of a DNA damage nidus. In Chapter 3, as our circuit newly permits temporal separation of damage and repair, we utilize our circuit to probe the kinetics of UV-mediated cell death and the timeframe in which repair must occur to prevent lethality. We find delaying SOS activation results in a rapid time-dependent loss of viability and global promoter silencing, and that the rate of irreversible lethality is energy-dependent but protein synthesis- and replication-independent, shedding light on the potential mechanisms of UV-mediated cell death. Finally, in Chapter 4, we outline future uses for our synthetic circuit to dissect the roles of the SOS pathway in repair, mutagenesis, and other phenotypes

Low-power emerging memristive designs towards secure hardware systems for applications in internet of things

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and in-memory computing (IMC), but there is a rising interest in using memristive technologies for security applications in the era of internet of things (IoT). In this review article, for achieving secure hardware systems in IoT, low-power design techniques based on emerging memristive technology for hardware security primitives/systems are presented. By reviewing the state-of-the-art in three highlighted memristive application areas, i.e. memristive non-volatile memory, memristive reconfigurable logic computing and memristive artificial intelligent computing, their application-level impacts on the novel implementations of secret key generation, crypto functions and machine learning attacks are explored, respectively. For the low-power security applications in IoT, it is essential to understand how to best realize cryptographic circuitry using memristive circuitries, and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security. This review article aims to help researchers to explore security solutions, to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs