A FEASIBILITY STUDY OF HIGH-VOLTAGE COMPARATORS USING SILICON METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

The overall trend of transistor scaling has resulted in distinct, application-specific manufacturing processes. Two of these specialized devices scaled complementary metal-oxide-semiconductor field-effect transistors (CMOS) and power transistors, typically have inversely related performance in speed, power handling, and size. This work develops a novel comparator circuit to explore the potential benefits of integrating these two technology schemes to achieve improved power handling capabilities for signal processing and communication systems through the development of a Silicon-based high-voltage comparator. The study produced a final circuit with a flat-band gain of 20dB across the high frequency (HF) range with a projected input voltage tolerance above 10V. The development process indicates that the physical characteristics of the power transistor, a laterally-diffused MOSFET (LDMOS), constrains frequency response and therefore, ultimately, comparator performance. Although the demonstrated device does not achieve the target performance, the investigation suggests that integrating the power transistors at the integrated circuit (IC) level is a promising approach to producing a competitive high-voltage Silicon-based comparator.M.S

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

Design and Applications of Minimally Invasive All-Pole Analog Filters

A new design technique for minimally invasive all-pole analog lowpass filters is introduced and the concept of minimally invasive filtering has been generalized for higher orders both in voltage-mode and current-mode operations. The proposed fully differential solution has minimal impact on the in-band signal in terms of added noise and nonlinearity, whereas it has comparable performance for out-of-band signals using smaller number of active devices. Extending the concept of current-mode minimally invasive filters, a novel baseband circuit with third order filtering has been designed, which has comparable linearity and noise with approximately half the power consumption when compared to the conventional solution. The proposed baseband circuit has a bandwidth of 10MHz, achieves 44dB rejection at 50MHz (40dB in post-layout simulations), low broad-band input impedance of 10.16ohm with a comparable noise and linearity at a lower power consumption when compared to a third order conventional circuit. The circuit has been designed in TSMC 130nm technology and is integrated with a broad-band receiver front-end including an LNA and a mixer

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

AC Power Combining Strategy with Application to Efficient Linear Power Amplifiers

With the ongoing push for wireless systems to accommodate more users and support higher data rates more efficient modulation schemes have been created that are more advanced than simple FM and AM modulation used for radio broadcasting. These modulation schemes, such as orthogonal frequency division multiplexing (OFDM), suffer from high peak to average power ratios. Standard Class A and Class AB amplifiers cannot simultaneously achieve good linearity and efficiency, and therefore there has been an increase in the development of new topologies to combat this issue. Common features to these circuits is power combining of two or more separate transistors. In this work, we consider various ways of two-source power combining and identify four topologies of interest. We notice that linear power-efficient amplifiers reported to date are based upon two of the identified combining strategies. We believe that no amplifiers have been reported that leverage the other two alternatives. This work produces a fully-functional amplifier based on one of these alternatives. The prototypes are intended to serve as concept verification of the architecture and hence are implemented at lower (1 MHz) frequencies

Low-power transceiver design for mobile wireless chemical biological sensors

The design of a smart integrated chemical sensor system that will enhance sensor performance and compatibility to Ad hoc network architecture remains a challenge. This work involves the design of a Transceiver for a mobile chemical sensor. The transceiver design integrates all building blocks on-chip, including a low-noise amplifier with an input-matching network, a Voltage Controlled Oscillator with injection locking, Gilbert cell mixers, and a Class E Power amplifier making it as a single-chip transceiver. This proposed low power 2GHz transceiver has been designed in TSMC 0.35~lm CMOS process using Cadence electronic design automation tools. Post layout HSPICE simulation indicates that Design meets the separation of noise levels by 52dB and 42dB in transmitter and receiver respectively with power consumption of 56 mW and 38 mW in transmit and receive mode