7 research outputs found
A Multi-objective Simulation Based Tool: Application to the Design of High Performance LC-VCOs
Part 16: Optimization Techniques in EnergyInternational audienceThe continuing size reduction of electronic devices imposes design challenges to optimize the performances of modern electronic systems, such as: wireless services, telecom and mobile computing. Fortunately, those design challenges can be overcome thanks to the development of Electronic Design Automation (EDA) tools. In the analog, mixed signal and radio-frequency (AMS/RF) domains, circuit optimization tools have demonstrated their usefulness in addressing design problems taking into account downscaling technological aspects. Recent advances in EDA have shown that the simulation-based sizing technique is a very interesting solution to the âcomplexâ modelling task in the circuit design optimization problem. In this paper we propose a multi-objective simulation-based optimization tool. A CMOS LC-VCO circuit is presented to show the viability of this tool. The tool is used to generate the Pareto front linking two conflicting objectives, namely the VCO Phase Noise and Power Consumption. The accuracy of the results is checked against HSPICE/RF simulations
Low Voltage Low Power Analogue Circuits Design
DisertaÄnĂ prĂĄce je zamÄĆena na vĂœzkum nejbÄĆŸnÄjĆĄĂch metod, kterĂ© se vyuĆŸĂvajĂ pĆi nĂĄvrhu analogovĂœch obvodĆŻ s vyuĆŸitĂ nĂzkonapÄĆ„ovĂœch (LV) a nĂzkopĆĂkonovĂœch (LP) struktur. Tyto LV LP obvody mohou bĂœt vytvoĆeny dĂky vyspÄlĂœm technologiĂm nebo takĂ© vyuĆŸitĂm pokroÄilĂœch technik nĂĄvrhu. DisertaÄnĂ prĂĄce se zabĂœvĂĄ prĂĄvÄ pokroÄilĂœmi technikami nĂĄvrhu, pĆedevĆĄĂm pak nekonvenÄnĂmi. Mezi tyto techniky patĆĂ vyuĆŸitĂ prvkĆŻ s ĆĂzenĂœm substrĂĄtem (bulk-driven - BD), s plovoucĂm hradlem (floating-gate - FG), s kvazi plovoucĂm hradlem (quasi-floating-gate - QFG), s ĆĂzenĂœm substrĂĄtem s plovoucĂm hradlem (bulk-driven floating-gate - BD-FG) a s ĆĂzenĂœm substrĂĄtem s kvazi plovoucĂm hradlem (quasi-floating-gate - BD-QFG). PrĂĄce je takĂ© orientovĂĄna na moĆŸnĂ© zpĆŻsoby implementace znĂĄmĂœch a modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m nebo mix-mĂłdu. Mezi tyto prvky lze zaÄlenit zesilovaÄe typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za ĂșÄelem potvrzenĂ funkÄnosti a chovĂĄnĂ vĂœĆĄe zmĂnÄnĂœch struktur a prvkĆŻ byly vytvoĆeny pĆĂklady aplikacĂ, kterĂ© simulujĂ usmÄrĆovacĂ a induktanÄnĂ vlastnosti diody, dĂĄle pak filtry dolnĂ propusti, pĂĄsmovĂ© propusti a takĂ© univerzĂĄlnĂ filtry. VĆĄechny aktivnĂ prvky a pĆĂklady aplikacĂ byly ovÄĆeny pomocĂ PSpice simulacĂ s vyuĆŸitĂm parametrĆŻ technologie 0,18 m TSMC CMOS. Pro ilustraci pĆesnĂ©ho a ĂșÄinnĂ©ho chovĂĄnĂ struktur je v disertaÄnĂ prĂĄci zahrnuto velkĂ© mnoĆŸstvĂ simulaÄnĂch vĂœsledkĆŻ.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the nonâconventional ones which are bulkâdriven (BD), floatingâgate (FG), quasiâfloatingâgate (QFG), bulkâdriven floatingâgate (BDâFG) and bulkâdriven quasiâfloatingâgate (BDâQFG) techniques. The thesis also looks at ways of implementing structures of wellâknown and modern active elements operating in voltageâ, currentâ, and mixedâmode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fullyâdifferential second generation current conveyor (FBâCCII), fullyâbalanced differential difference amplifier (FBâDDA), voltage differencing transconductance amplifier (VDTA), currentâcontrolled current differencing buffered amplifier (CCâCDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diodeâless rectifier and inductance simulations, as well as lowâpass, bandâpass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.
New Possibilities In Low-voltage Analog Circuit Design Using Dtmos Transistors
(Doktora) -- Ä°stanbul Teknik Ăniversitesi, Fen Bilimleri EnstitĂŒsĂŒ, 2013(PhD) -- Ä°stanbul Technical University, Institute of Science and Technology, 2013Bu çalıĆmada DTMOS yaklaĆımı çok dĂŒĆĂŒk besleme gerilimlerinde çalıĆan çok dĂŒĆĂŒk gĂŒĂ§ tĂŒketimli devrelere baĆarıyla uygulanmıĆtır. Tasarlanan devreler arasında OTA, OP-AMP, CCII gibi analog aktif yapı blokları, çarpma devresi, sadece-MOS yapılar gibi devreler bulunmaktadır. Tasarlanan devreler SPICE benzetimleri ile doÄrulanmıĆtır. Ä°leri yönde gövde kutuplamaya baÄlı olarak DTMOS transistorun yapısından kaynaklanan, efektif olarak dĂŒĆĂŒk eĆik gerilimli çalıĆma özelliÄi nedeniyle, çok dĂŒĆĂŒk gĂŒĂ§ tĂŒketimli ve çok dĂŒĆĂŒk gerilimli devrelerde DTMOS yaklaĆımının geçerli bir alternatif olduÄu bu çalıĆmayla gösterilmiĆtir. DTMOS yaklaĆımının geniĆ bir alanda çeĆitlilik gösteren analog devre yapılarında çok dĂŒĆĂŒk besleme gerilimlerinde bile kabul edilebilir bir performansla kullanılabileceÄi bulunmuĆtur.In this study, DTMOS approach to the design of ultra low-voltage and ultra low-power analog circuits, has been successfully applied to the circuits ranging from EEG filtering circuits, speech processing filters in hearing aids, multipliers, analog active building blocks: OTA, OP-AMP, CCII to MOS-only circuits. The proposed circuits are verified with SPICE simulations. It is found that in designing ultra low-voltage, ultra low-power analog circuits, DTMOS approach is a viable alternative due to its inherent characteristic of effective low threshold voltage behaviour under forward body bias. This approach can be applied to several analog application subjects with acceptable performance under even ultra low supply voltages.DoktoraPh
CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices
La rĂĄpida evoluciĂłn en el campo de los sensores inteligentes, junto con los avances en las tecnologĂas de la computaciĂłn y la comunicaciĂłn, estĂĄ revolucionando la forma en que recopilamos y analizamos datos del mundo fĂsico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusiĂłn en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorizaciĂłn y actuaciĂłn ha sido posible gracias a los avances en micro (y nano) electrĂłnica. Al mismo tiempo, la evoluciĂłn de las tecnologĂas de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementaciĂłn de matrices de sensores de alta densidad. AsĂ, la combinaciĂłn de un sistema de adquisiciĂłn basado en sensores on-Chip, junto con un microprocesador como nĂșcleo digital donde se puede ejecutar la digitalizaciĂłn de señales, el procesamiento y la comunicaciĂłn de datos proporciona caracterĂsticas adicionales como reducciĂłn del coste, compacidad, portabilidad, alimentaciĂłn por baterĂa, facilidad de uso e intercambio inteligente de datos, aumentando su potencial nĂșmero de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portĂĄtil de mediciĂłn de espectroscopĂa de impedancia de baja potencia operado por baterĂa, basado en tecnologĂas microelectrĂłnicas CMOS, que pueda integrarse con el sensor, proporcionando una implementaciĂłn paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales caracterĂsticas de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestiĂłn de la energĂa como de las diferentes celdas que conforman la interfaz, que habrĂĄn de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mĂnimo y bajo consumo requeridas en la monitorizaciĂłn portĂĄtil, caracterĂsticas que son aĂșn mĂĄs crĂticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caĂda de voltaje como unidad de gestiĂłn de energĂa, que proporciona una alimentaciĂłn de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentaciĂłn con una aproximaciĂłn completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulaciĂłn dual, que estĂĄ embebido en el amplificador para optimizar consumo y ĂĄrea; y filtros pasa baja totalmente integrados, que actĂșan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /
An Optimization Theoretical Framework for Resource Allocation over Wireless Networks
With the advancement of wireless technologies, wireless networking has become ubiquitous owing to the great demand of pervasive mobile applications. Some fundamental challenges exist for the next generation wireless network design such as time varying nature of wireless channels, co-channel interferences, provisioning of heterogeneous type of services, etc. So how to overcome these difficulties and improve the system performance have become an important research topic.
Dynamic resource allocation is a general strategy to control the interferences and enhance the performance of wireless networks. The basic idea behind dynamic resource allocation is to utilize the channel more efficiently by sharing the spectrum and reducing
interference through optimizing parameters such as the
transmitting power, symbol transmission rate, modulation scheme, coding scheme, bandwidth, etc. Moreover, the network performance can be further improved by introducing diversity, such as
multiuser, time, frequency, and space diversity. In addition, cross layer approach for resource allocation can provide advantages such as low overhead, more efficiency, and direct end-to-end QoS provision.
The designers for next generation wireless networks face the common problem of how to optimize the system objective under the user Quality of Service (QoS) constraint. There is a need of unified but general optimization framework for resource allocation
to allow taking into account a diverse set of objective functions with various QoS requirements, while considering all kinds of diversity and cross layer approach. We propose an optimization
theoretical framework for resource allocation and apply these ideas to different network situations such as:
1.Centralized resource allocation with fairness constraint
2.Distributed resource allocation using game theory
3.OFDMA resource allocation
4.Cross layer approach
On the whole, we develop a universal view of the whole wireless networks from multiple dimensions: time, frequency, space, user, and layers. We develop some schemes to fully utilize the resources. The success of the proposed research will significantly
improve the way how to design and analyze resource allocation over wireless networks. In addition, the cross-layer optimization nature of the problem provides an innovative insight into vertical
integration of wireless networks
CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications
Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non-
Linear (ELIN) systems. They can handle large-signals in a low power environment under half
the capacitor area required by the more popular ELIN Log-domain filters. Their inherent
class-AB nature stems from the odd property of the sinh function at the heart of their
companding operation. Despite this early realisation, the Sinh filtering paradigm has not
attracted the interest it deserves to date probably due to its mathematical and circuit-level
complexity.
This Thesis presents an overview of the CMOS weak inversion Sinh filtering
paradigm and explains how biomedical systems of low- to audio-frequency range could
benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of
high order Sinh continuousâtime filters and more importantly to confirm their micro-power
consumption and 100+ dB of DR through measured results presented for the first time.
Novel high order Sinh topologies are designed by means of a systematic
mathematical framework introduced. They employ a recently proposed CMOS Sinh
integrator comprising only p-type devices in its translinear loops. The performance of the
high order topologies is evaluated both solely and in comparison with their Log domain
counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a
corresponding and also novel Log domain class-AB topology, confirming that Sinh filters
constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense
of higher complexity and power consumption. The theoretical findings are validated by
means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a
0.35ÎŒm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of
~60dB and 74ÎŒW power consumption from 2V power supply