A Study of MPPT Charge Controller Roles in Photovoltaic Energy Management

Energy management system for controlling a microgrid. Management of power flow for minimizing the cost of electricity and reduction of loss of energy produced by renewable energy sources. This paper is about a study of MPPT charge controller roles in photovoltaic energy management. PV systems usually provide a photovoltaic array, the MPPT charge controller, storage battery, and dc load. The MPPT charge controller is important. It continuously tracks the maximum power point and delivers the maximum possible power to the battery at any given point in time. In this project, a dc-dc boost converter circuit has been simulated using the software of Proteus. The microcontroller in Arduino NANO is used and will read the voltage values, the current values, and process all the calculations. Perturb and observe (P & O) algorithm is used to transfer maximum power from the PV panel which is executed using a microcontroller. The Arduino NANO is programmed using the software of Arduino IDE. Liquid Crystal Display (LCD) is used to display the voltage, current, and power from the PV module and PWM from the MPPT charge controller. The benefit of this project is to achieve high efficiency and low cost of photovoltaic (PV) model for the design of PV systems with a simple MPPT

Design & Evaluation of a Hybrid Switched Capacitor Circuit with Wide-Bandgap Devices for DC Grid Applications

ABSTRACT As technologies advance, the rate at which renewable power sources, such as solar photovoltaic (PV) and wind, are being added to the power grid is increasing. Typically, PV power plants require large inverters for direct current to alternating current (DC-AC) power conversion, as well as large transformers to step up voltages to the grid voltage. Offshore wind farms and large PV power plants in remote locations often aggregate power on a DC bus in order to improve efficiency and reduce the cost of power conversion hardware within the energy complex. However, the power must still be converted to AC for integration into the grid. Research is being done to allow greater adoption of low, medium, and high voltage DC distribution, wherein DC power is used directly by loads. This has the potential for additional cost savings. To better realize this vision, however, new DC-DC converter technologies must be developed that are small, cheap and efficient at the voltages and power levels relevant to grid integrations. This project demonstrates the feasibility of a switched capacitor boost converter topology that is scalable to 10 kilovolts, and can serve as an interface between lower voltage PV arrays and medium voltage DC (MVDC) distribution lines. In particular, this approach relies on switched capacitors, wide-bandgap (WGB) devices, and high-frequency switching to achieve high power density and high gain. As part of this work, two prototypes were constructed including a benchtop-scale prototype rated for 25W at 500 Volts and a 6 kW 10 kV converter. In particular, this second converter was demonstrated in hardware to deliver 2.56 kW at 10 kV DC to a resistive load with greater than 95% efficiency, demonstrating the feasibility of this converter for grid applications

Fault Resilient and Reconfigurable Power Management Using Photovoltaic Integrated with CMOS Switches

A Photovoltaic (PV) cell is a device which converts light incident upon it to electric current. The push for green energy due to global warming and diminution of fossil fuels opens up a huge market for PV cells. Hence, a lot of interest is being garnered for using PV cells for various applications. However, a PV module\u27s performance degrades due to many anomalies such as failure of individual PV cell within a module, the opening of interconnection, a short circuit in the connection, failure of bypass diode, failure in voltage regulator or partial shading. To some extent all of these issues can be addressed by introducing a transistor as a switch in a PV module. This kind of architecture also enables the PV module to switch between high voltage with low current or high current with low voltage. Moreover, such architecture is handy when PV modules are deployed at remote locations where manual intervention in the case of fault or power management becomes too expensive or impossible. With advancements in semiconductor processing, the MOSFET switches can now be integrated with a PV cell for improved reliability. In this research project, we introduced addressable switches for PV cell that enable the creation of real-time reconfigurable power buses or power island. Moreover, for PV module deployed at a remote location, we have installed an architecture that let the PV module self-detect faulty PV cells or partial shading condition. Such algorithms detect faulty PV cells or PV cells under partial shading within the module such that the performance of the PV module does not become degraded. The algorithms actively use an embedded computing device to predict the output power based on a number of PV cells connected in series and parallel; then the computed power is compared with the measured power for faulty condition detection. Typically, for achieving such kind of computing architecture a single-diode based PV module modeling technique is used. However, all of these modeling techniques have an exponential term due to the presence of a diode, the computing of output power and performance of PV module becomes power intensive and it is difficult to implement on an embedded system. Also, due to the presence of the exponential term, there is no closed form solution for IPV versus VPV (output current of PV cell versus output voltage of a PV cell). We have introduced a PV module modeling using an N-channel MOSFET transistor that doesn\u27t have an exponential term. Moreover, a quadratic equation based solution is obtained that can be solved for calculating the load current. Using the same technique PV module can be also be modeled for various configuration. Additionally, with MOSFET based PV cells modeling enables the modeling CMOS-with-PV which is also presented in this work

Fast spatially-resolved electrical modelling and quantitative characterisation of photovoltaic devices

An efficient and flexible modelling and simulation toolset for solving spatially-resolved models of photovoltaic (PV) devices is developed, and its application towards a quantitative description of localised electrical behaviour is given. A method for the extraction of local electrical device parameters is developed as a complementary approach to the conventional characterisation techniques based on lumped models to meet the emerging demands of quantitative spatially-resolved characterisation in the PV community. It allows better understanding of the effects of inhomogeneities on performance of PV devices. The simulation tool is named PV-Oriented Nodal Analysis (PVONA). This is achieved by integrating a specifically designed sparse data structure and a graphics processing unit (GPU)-based parallel conjugate gradient algorithm into a PV-oriented numerical solver. It allows more efficient high-resolution spatially-resolved modelling and simulations of PV devices than conventional approaches based on SPICE (Simulation Program with Integrated Circuit Emphasis) tools in terms of computation time and memory usage. In tests, mega-sub-cell level test cases failed in the latest LTSpice version (v4.22) and a PSpice version (v16.6) on desktop PCs with mainstream hardware due to a memory shortage. PVONA efficiently managed to solve the models. Moreover, it required up to only 5% of the time comparing the two SPICE counterparts. This allows the investigation of inhomogeneities and fault mechanisms in PV devices with high resolution on common computing platforms. The PVONA-based spatially-resolved modelling and simulation is used in various purposes. As an example, it is utilised to evaluate the impacts of nonuniform illumination profiles in a concentrator PV unit. A joint optical and electrical modelling framework is presented. Simulation results suggest that uncertainties introduced during the manufacturing and assembly of the optical components can significantly affect the performance of the system in terms of local voltage and current distribution and global current-voltage characteristics. Significant series resistance and shunt resistance effects are found to be caused by non-uniformity irradiance profiles and design parameters of PV cells. The potential of utilising PVONA as a quality assessment tool for system design is discussed. To achieve quantitative characterisation, the PVONA toolset is then used for developing a 2-D iterative method for the extraction of local electrical parameters of spatially-resolved models of thin-film devices. The method employs PVONA to implement 2-D fitting to reproduce the lateral variations in electroluminescence (EL) images, and to match the dark current-voltage characteristic simultaneously to compensate the calibration factor in EL characterisations. It managed to separate the lateral resistance from the overall series resistance effects. The method is verified by simulations. Experimental results show that pixellation of EL images can be achieved. Effects of local shunts are accurately reproduced by a fitting algorithm. The outcomes of this thesis provide valuable tools that can be used as a complementary means of performance evaluation of PV devices. After proper optimisation, these tools can be used to assist various analysis tasks during the whole lifecycle of PV products

Increasing the capacity of the Low Voltage Distribution Networks using All-SiC AC-AC Converters

Towards 2020, future energy scenarios predict an excessive penetration of distributed generation (DG) in low voltage (LV) networks as well as a significant uptake of electric vehicles (EVs) and electro-heating. The Distribution Network Operators (DNOs) in UK will face significant challenges towards this de-carbonised electricity generation and consumption shift. The deployment of these so-called low carbon technologies (LCTs) will impact the performance of the distribution network in such way where solutions will be needed to maintain capacity, reliability and the availability of the electricity supply to customers. The practise to put more copper on the ground – reinforcement - in order to facilitate these changes is found to be expensive and disruptive to the public and business. An innovative solution proposed in this thesis is to increase the voltage along the distribution feeders and step it back down at a customer’s premises. Results show that a significant increase at the hosting capacity of the existing network can be achieved and power quality problems such as overvoltage caused by DG can be avoided. The voltage step-down device, which is termed a voltage control unit (VCU), is to be located in the meter-box of each house. This location raises challenges round the temperature rise in the box caused by VCU losses, and the subsequent effect on the electricity meter and cut-out fuse. It also imposes constraints on the size and weight of the VCU so that a very high efficiency design is required, with high power density and small mass. The optimum VCU design was found to be a power electronic AC Chopper using new Silicon Carbide (SiC) MOSFETs and diodes. The technology was demonstrated by designing, constructing and testing two interleaved, parallel operation, 1 kW AC Chopper modules. Results from the prototype were compared against Spice simulation results and theory and confirmed that the target efficiency of 99% was achieved

A Viable Residential DC Microgrid for Low Income Communities – Architecture, Protection and Education

The availability of fossil fuels in the future and the environmental effects such as the carbon footprint of the existing methodologies to produce electricity is an increasing area of concern. In rural areas of under-developed parts of the world, the problem is lack of access to electrification. DC microgrids have become a proven solution to electrification in these areas with demonstrated exceptional quality of power, high reliability, efficiency, and simplified integration between renewable energy sources (principally solar PV) and energy storage. In the United States, a different problem occurs that can be addressed with the same DC microgrid approach that is finding success internationally. In disinvested, underserved communities with high unemployment and low wages, households contribute a significant portion of their income towards the fixed cost of their electrical utility connection, which by law must be supplied to every household. In order to realize such a microgrid in these communities, there are three major areas which need to be accounted for. Firstly, there needs to be a custom architecture for the community under consideration and it needs to be economical to match the needs of the underserved community. Secondly, DC microgrid for home energy interconnection is potentially less complex and less expensive to deploy, operate and maintain however, faster protection is a key element to ensuring resilience, viability and adoptability. Lastly, these types of efforts will be sustainable only if the people in the community are educated and invested in the same as they are the key stakeholders in these systems. This dissertation presents an approach to make the DC Microgrid economically feasible for low income households by reducing the cost they incur on electric bills. The approach is to overlay a DC system into homes that have a utility feed in order to incorporate renewable energy usage into an urban setting for the express purpose of driving down individual household utility costs. The results show that the incorporation of a certain level of “smart” appliances and fixtures into the renovation of vacated homes and the use of a microgrid to enable sharing of renewable energy, such as solar power combined with energy storage, between homes in the proposed architecture yields the least expensive option for the patrons. The development of solid state circuit breakers that interface between the microgrid and the home DC power panels helps in faster protection of the DC system. In this dissertation, a SiC JFET based device is designed and built to protect against DC faults at a faster rate than the available solutions. The prototype is tested for verification and used to discriminate against short circuit faults and the results show the successful fault discrimination capabilities of the device. A basic system level simulation with the protection device is implemented using Real Time Hardware in the loop platform. Finally, as a part of engaging the community members, the high school kids in the area who might potentially be living in some of the houses in this community are being educated about the microgrid, appliances and other technologies to get a better understanding of STEM and hopefully inspiring them to pursue a career in STEM in the future

A Viable Residential DC Microgrid for Low Income Communities – Architecture, Protection and Education

The availability of fossil fuels in the future and the environmental effects such as the carbon footprint of the existing methodologies to produce electricity is an increasing area of concern. In rural areas of under-developed parts of the world, the problem is lack of access to electrification. DC microgrids have become a proven solution to electrification in these areas with demonstrated exceptional quality of power, high reliability, efficiency, and simplified integration between renewable energy sources (principally solar PV) and energy storage. In the United States, a different problem occurs that can be addressed with the same DC microgrid approach that is finding success internationally. In disinvested, underserved communities with high unemployment and low wages, households contribute a significant portion of their income towards the fixed cost of their electrical utility connection, which by law must be supplied to every household. In order to realize such a microgrid in these communities, there are three major areas which need to be accounted for. Firstly, there needs to be a custom architecture for the community under consideration and it needs to be economical to match the needs of the underserved community. Secondly, DC microgrid for home energy interconnection is potentially less complex and less expensive to deploy, operate and maintain however, faster protection is a key element to ensuring resilience, viability and adoptability. Lastly, these types of efforts will be sustainable only if the people in the community are educated and invested in the same as they are the key stakeholders in these systems. This dissertation presents an approach to make the DC Microgrid economically feasible for low income households by reducing the cost they incur on electric bills. The approach is to overlay a DC system into homes that have a utility feed in order to incorporate renewable energy usage into an urban setting for the express purpose of driving down individual household utility costs. The results show that the incorporation of a certain level of “smart” appliances and fixtures into the renovation of vacated homes and the use of a microgrid to enable sharing of renewable energy, such as solar power combined with energy storage, between homes in the proposed architecture yields the least expensive option for the patrons. The development of solid state circuit breakers that interface between the microgrid and the home DC power panels helps in faster protection of the DC system. In this dissertation, a SiC JFET based device is designed and built to protect against DC faults at a faster rate than the available solutions. The prototype is tested for verification and used to discriminate against short circuit faults and the results show the successful fault discrimination capabilities of the device. A basic system level simulation with the protection device is implemented using Real Time Hardware in the loop platform. Finally, as a part of engaging the community members, the high school kids in the area who might potentially be living in some of the houses in this community are being educated about the microgrid, appliances and other technologies to get a better understanding of STEM and hopefully inspiring them to pursue a career in STEM in the future

Degradation Models and Optimizations for CMOS Circuits

Die Gewährleistung der Zuverlässigkeit von CMOS-Schaltungen ist derzeit eines der größten Herausforderungen beim Chip- und Schaltungsentwurf. Mit dem Ende der Dennard-Skalierung erhöht jede neue Generation der Halbleitertechnologie die elektrischen Felder innerhalb der Transistoren. Dieses stärkere elektrische Feld stimuliert die Degradationsphänomene (Alterung der Transistoren, Selbsterhitzung, Rauschen, usw.), was zu einer immer stärkeren Degradation (Verschlechterung) der Transistoren führt. Daher erleiden die Transistoren in jeder neuen Technologiegeneration immer stärkere Verschlechterungen ihrer elektrischen Parameter. Um die Funktionalität und Zuverlässigkeit der Schaltung zu wahren, wird es daher unerlässlich, die Auswirkungen der geschwächten Transistoren auf die Schaltung präzise zu bestimmen. Die beiden wichtigsten Auswirkungen der Verschlechterungen sind ein verlangsamtes Schalten, sowie eine erhöhte Leistungsaufnahme der Schaltung. Bleiben diese Auswirkungen unberücksichtigt, kann die verlangsamte Schaltgeschwindigkeit zu Timing-Verletzungen führen (d.h. die Schaltung kann die Berechnung nicht rechtzeitig vor Beginn der nächsten Operation abschließen) und die Funktionalität der Schaltung beeinträchtigen (fehlerhafte Ausgabe, verfälschte Daten, usw.). Um diesen Verschlechterungen der Transistorparameter im Laufe der Zeit Rechnung zu tragen, werden Sicherheitstoleranzen eingeführt. So wird beispielsweise die Taktperiode der Schaltung künstlich verlängert, um ein langsameres Schaltverhalten zu tolerieren und somit Fehler zu vermeiden. Dies geht jedoch auf Kosten der Performanz, da eine längere Taktperiode eine niedrigere Taktfrequenz bedeutet. Die Ermittlung der richtigen Sicherheitstoleranz ist entscheidend. Wird die Sicherheitstoleranz zu klein bestimmt, führt dies in der Schaltung zu Fehlern, eine zu große Toleranz führt zu unnötigen Performanzseinbußen. Derzeit verlässt sich die Industrie bei der Zuverlässigkeitsbestimmung auf den schlimmstmöglichen Fall (maximal gealterter Schaltkreis, maximale Betriebstemperatur bei minimaler Spannung, ungünstigste Fertigung, etc.). Diese Annahme des schlimmsten Falls garantiert, dass der Chip (oder integrierte Schaltung) unter allen auftretenden Betriebsbedingungen funktionsfähig bleibt. Darüber hinaus ermöglicht die Betrachtung des schlimmsten Falles viele Vereinfachungen. Zum Beispiel muss die eigentliche Betriebstemperatur nicht bestimmt werden, sondern es kann einfach die schlimmstmögliche (sehr hohe) Betriebstemperatur angenommen werden. Leider lässt sich diese etablierte Praxis der Berücksichtigung des schlimmsten Falls (experimentell oder simulationsbasiert) nicht mehr aufrechterhalten. Diese Berücksichtigung bedingt solch harsche Betriebsbedingungen (maximale Temperatur, etc.) und Anforderungen (z.B. 25 Jahre Betrieb), dass die Transistoren unter den immer stärkeren elektrischen Felder enorme Verschlechterungen erleiden. Denn durch die Kombination an hoher Temperatur, Spannung und den steigenden elektrischen Feldern bei jeder Generation, nehmen die Degradationphänomene stetig zu. Das bedeutet, dass die unter dem schlimmsten Fall bestimmte Sicherheitstoleranz enorm pessimistisch ist und somit deutlich zu hoch ausfällt. Dieses Maß an Pessimismus führt zu erheblichen Performanzseinbußen, die unnötig und demnach vermeidbar sind. Während beispielsweise militärische Schaltungen 25 Jahre lang unter harschen Bedingungen arbeiten müssen, wird Unterhaltungselektronik bei niedrigeren Temperaturen betrieben und muss ihre Funktionalität nur für die Dauer der zweijährigen Garantie aufrechterhalten. Für letzteres können die Sicherheitstoleranzen also deutlich kleiner ausfallen, um die Performanz deutlich zu erhöhen, die zuvor im Namen der Zuverlässigkeit aufgegeben wurde. Diese Arbeit zielt darauf ab, maßgeschneiderte Sicherheitstoleranzen für die einzelnen Anwendungsszenarien einer Schaltung bereitzustellen. Für fordernde Umgebungen wie Weltraumanwendungen (wo eine Reparatur unmöglich ist) ist weiterhin der schlimmstmögliche Fall relevant. In den meisten Anwendungen, herrschen weniger harsche Betriebssbedingungen (z.B. sorgen Kühlsysteme für niedrigere Temperaturen). Hier können Sicherheitstoleranzen maßgeschneidert und anwendungsspezifisch bestimmt werden, sodass Verschlechterungen exakt toleriert werden können und somit die Zuverlässigkeit zu minimalen Kosten (Performanz, etc.) gewahrt wird. Leider sind die derzeitigen Standardentwurfswerkzeuge für diese anwendungsspezifische Bestimmung der Sicherheitstoleranz nicht gut gerüstet. Diese Arbeit zielt darauf ab, Standardentwurfswerkzeuge in die Lage zu versetzen, diesen Bedarf an Zuverlässigkeitsbestimmungen für beliebige Schaltungen unter beliebigen Betriebsbedingungen zu erfüllen. Zu diesem Zweck stellen wir unsere Forschungsbeiträge als vier Schritte auf dem Weg zu anwendungsspezifischen Sicherheitstoleranzen vor: Schritt 1 verbessert die Modellierung der Degradationsphänomene (Transistor-Alterung, -Selbsterhitzung, -Rauschen, etc.). Das Ziel von Schritt 1 ist es, ein umfassendes, einheitliches Modell für die Degradationsphänomene zu erstellen. Durch die Verwendung von materialwissenschaftlichen Defektmodellierungen werden die zugrundeliegenden physikalischen Prozesse der Degradationsphänomena modelliert, um ihre Wechselwirkungen zu berücksichtigen (z.B. Phänomen A kann Phänomen B beschleunigen) und ein einheitliches Modell für die simultane Modellierung verschiedener Phänomene zu erzeugen. Weiterhin werden die jüngst entdeckten Phänomene ebenfalls modelliert und berücksichtigt. In Summe, erlaubt dies eine genaue Degradationsmodellierung von Transistoren unter gleichzeitiger Berücksichtigung aller essenziellen Phänomene. Schritt 2 beschleunigt diese Degradationsmodelle von mehreren Minuten pro Transistor (Modelle der Physiker zielen auf Genauigkeit statt Performanz) auf wenige Millisekunden pro Transistor. Die Forschungsbeiträge dieser Dissertation beschleunigen die Modelle um ein Vielfaches, indem sie zuerst die Berechnungen so weit wie möglich vereinfachen (z.B. sind nur die Spitzenwerte der Degradation erforderlich und nicht alle Werte über einem zeitlichen Verlauf) und anschließend die Parallelität heutiger Computerhardware nutzen. Beide Ansätze erhöhen die Auswertungsgeschwindigkeit, ohne die Genauigkeit der Berechnung zu beeinflussen. In Schritt 3 werden diese beschleunigte Degradationsmodelle in die Standardwerkzeuge integriert. Die Standardwerkzeuge berücksichtigen derzeit nur die bestmöglichen, typischen und schlechtestmöglichen Standardzellen (digital) oder Transistoren (analog). Diese drei Typen von Zellen/Transistoren werden von der Foundry (Halbleiterhersteller) aufwendig experimentell bestimmt. Da nur diese drei Typen bestimmt werden, nehmen die Werkzeuge keine Zuverlässigkeitsbestimmung für eine spezifische Anwendung (Temperatur, Spannung, Aktivität) vor. Simulationen mit Degradationsmodellen ermöglichen eine Bestimmung für spezifische Anwendungen, jedoch muss diese Fähigkeit erst integriert werden. Diese Integration ist eines der Beiträge dieser Dissertation. Schritt 4 beschleunigt die Standardwerkzeuge. Digitale Schaltungsentwürfe, die nicht auf Standardzellen basieren, sowie komplexe analoge Schaltungen können derzeit nicht mit analogen Schaltungssimulatoren ausgewertet werden. Ihre Performanz reicht für solch umfangreiche Simulationen nicht aus. Diese Dissertation stellt Techniken vor, um diese Werkzeuge zu beschleunigen und somit diese umfangreichen Schaltungen simulieren zu können. Diese Forschungsbeiträge, die sich jeweils über mehrere Veröffentlichungen erstrecken, ermöglichen es Standardwerkzeugen, die Sicherheitstoleranz für kundenspezifische Anwendungsszenarien zu bestimmen. Für eine gegebene Schaltungslebensdauer, Temperatur, Spannung und Aktivität (Schaltverhalten durch Software-Applikationen) können die Auswirkungen der Transistordegradation ausgewertet werden und somit die erforderliche (weder unter- noch überschätzte) Sicherheitstoleranz bestimmt werden. Diese anwendungsspezifische Sicherheitstoleranz, garantiert die Zuverlässigkeit und Funktionalität der Schaltung für genau diese Anwendung bei minimalen Performanzeinbußen

GPU NTC Process Variation Compensation with Voltage Stacking

Near-threshold computing (NTC) has the potential to significantly improve efficiency in high throughput architectures, such as general-purpose computing on graphic processing unit (GPGPU). Nevertheless, NTC is more sensitive to process variation (PV) as it complicates power delivery. We propose GPU stacking, a novel method based on voltage stacking, to manage the effects of PV and improve the power delivery simultaneously. To evaluate our methodology, we first explore the design space of GPGPUs in the NTC to find a suitable baseline configuration and then apply GPU stacking to mitigate the effects of PV. When comparing with an equivalent NTC GPGPU without PV management, we achieve 37% more performance on average. When considering high production volume, our approach shifts all the chips closer to the nominal non-PV case, delivering on average (across chips) ˜80 % of the performance of nominal NTC GPGPU, whereas when not using our technique, chips would have ˜50 % of the nominal performance. We also show that our approach can be applied on top of multifrequency domain designs, improving the overall performance