Characterisation and noise analysis of high Ge content p-channel SiGe MOSFETs fabricated using virtual substrates

This thesis demonstrates the advantages and disadvantages of investigated p-type SiGe MOSFETs with high Ge content Si1#xGex p-channel grown on Si1#yGey virtual substrate (VS) (x "0'7$0'9, y "0'3$0'5) in comparison with conventional Si devices. The ways to overcome current difficulties in conventional Si technology and mixed SiGe-Si technology are shown. Current-voltage (I-V) and capacitance-voltage (C-V) DC characteristics for p-channel Si/Si1#xGex/Si1#yGey hetero-MOSFETs with high Ge content (x "0'7$0'9, y"0'3$0'5) are reported. Enhancement in the maximum drain current for the p-SiGe devices in comparison with p-Si control is 2.5-3.0 times. DC characteristic simulations of SiGe p-channel MOSFETs were used to improve the accuracy of MOSFET and heterostructure parameters extraction. Calibrated during the simulation theoretical models were used for future design. The effective mobility, the source-drain access resistance, the doping profile, the layers thickness, oxide/semiconductor interface charge and other important characteristics were extracted. The effective mobility values, extracted for p-Si0%3Ge0%7 MOSFETs, exceed the hole mobility in a conventional Si p-MOS device by a factor of 3.5 and reach the mobility of conventional Si n-MOS transistors. The peak value of me f f = 760 cm2V#1s#1 at field 0.08 MVcm#1 was obtained for p-Si/Si0%2Ge0%8/ Si0%5Ge0%5 MOSFETs. Efficiency of special n-type doped layer, also known as "punch-through" stopper, introduced into heterostructure is shown. Perfect I-V and also low frequency noise characteristics of investigated MOSFET show that the p-type Si/Si1#xGex/Si1#yGey (x "0'7 $0'9, x$y "0'3$0'4) heterostructures with "punch-through" stopper could be very impressive opportunity to conventional Si for modern semiconductor industry. For the first time, quantitative explanation of the low frequency noise reduction in metamorphic, high Ge content, SiGe p-MOSFETs compared to Si p-MOSFETs have been proposed. Quantitative analysis demonstrates the importance of both carrier number fluctuations and correlated mobility fluctuations (CMF) components to the 1/ f noise of surface channel Si p-MOSFET, but the absence of CMF for buried channel p-Si0%3Ge0%7 and p- Si0%2Ge0%8 MOSFETs. The low frequency noise was measured to be three times smaller for a 0.55 mm effective gate length p-Si0%3Ge0%7 MOSFET than the Si control, at linear regime (VDS = -50 mV) and high gate overdrive voltage (Vgt= -1.5 V). This result is very important, because we have reduction in LF noise at high gate overdrive voltages, which are typical for analogue and power electronics application. Both DC and low frequency noise characteristics show that access source and drain resistance for metamorphic p-SiGe MOSFETs (RS +RD ,1.5-2.0kW !mm) roughly 2 times lower then for conventional p-Si MOSFETs

Broadband 300-GHz Power Amplifier MMICs in InGaAs mHEMT Technology

In this article, we report on compact solid-state power amplifier (SSPA) millimeter-wave monolithic integrated circuits (MMICs) covering the 280–330-GHz frequency range. The technology used is a 35-nm gate-length InGaAs metamorphic highelectron- mobility transistor (mHEMT) technology. Two power amplifier MMICs are reported, based on a compact unit amplifier cell, which is parallelized two times using two different Wilkinson power combiners. The Wilkinson combiners are designed using elevated coplanar waveguide and air-bridge thin-film transmission lines in order to implement low-loss 70-Ω lines in the back-endof-line of this InGaAs mHEMT technology. The five-stage SSPA MMICs achieve a measured small-signal gain around 20 dB over the 280–335-GHz frequency band. State-of-the-art output power performance is reported, achieving at least 13 dBm over the 286–310-GHz frequency band, with a peak output power of 13.7 dBm (23.4 mW) at 300 GHz. The PA MMICs are designed for a reduced chip width while maximizing the total gate width of 512 μm in the output stage, using a compact topology based on cascode and common-source devices, improving the output power per required chip width significantly

An Overview of Solid-State Integrated Circuit Amplifiers in the Submillimeter-Wave and THz Regime

We present an overview of solid-state integrated circuit amplifiers approaching terahertz frequencies based on the latest device technologies which have emerged in the past several years. Highlights include the best reported data from heterojunction bipolar transistor (HBT) circuits, high electron mobility transistor (HEMT) circuits, and metamorphic HEMT (mHEMT) amplifier circuits. We discuss packaging techniques for the various technologies in waveguide modules and describe the best reported noise figures measured in these technologies. A consequence of THz transistors, namely ultra-low-noise at cryogenic temperatures, will be explored and results presented. We also present a short review of power amplifier technologies for the THz regime. Finally, we discuss emerging materials for THz amplifiers into the next decade

The development of sub-25 nm III-V High Electron Mobility Transistors

High Electron Mobility Transistors (HEMTs) are crucially important devices in microwave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecommunications applications operating at frequencies well above 100 GHz. These new applications have driven demand for high frequency, low noise device operation; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance. Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years. This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam lithography and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described. This work has led to the successful fabrication of functional 22 nm HEMTs and the development of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes

Electrical Characterization of Integrated InAs Nano-Structures

This thesis analyzes the electrical properties of InAs nano-structures, that are integrated into different materials and geometries. The thesis describes integration related issues of InAs, the epitaxial synthesis of the InAs nano-structures and summarizes experimental techniques for analysis of electrical properties of the integrated structures. InAs thin films, nanowires and membranes are investigated to determine their electrical quality. The thin films (> 300 nm thick) are integrated onto GaAs substrates using overgrowth over the tungsten patterns. Such integration method allows varying the area of the surface pinning region within the material to measure the extent of this region in InAs. A carrier saturation is observed when the tungsten density is increased which allows determining the effective length of the surface pinning region to be under 400 nm. InAs nanowire capacitors are investigated to measure their doping density and doping profile. The capacitance of the nanowire capacitors exhibits non parabolic band behavior and a full depletion, in contrast to conventional MOS capacitors. The threshold voltage of the fully depleted nanowires is extracted to determine doping density and dopant distribution profile within a nanowire. It is shown that dopants incorporate preferentially at the nanowire surface and the surface doping concentration is higher than in the nanowire bulk. Also, capacitance transients are analyzed to show the presence of traps in the oxide. InAs metamorphic films are integrated onto GaSb buffer layer to evaluate the relation between the quality of the buffer layer and the InAs. It is observed, that metamorphic InAs membranes (23 nm thick) are highly resistive, while thicker membranes (90 nm thick) can be measured by Hall Effect measurements. The mobility of 90 nm membranes is found be 2700 cm^2/Vs, which indicates a loss of the metamorphic lattice. It is shown that the resistivity of thin membranes is highly sensitive to surface treatment

Enhancing hole mobility in III-V semiconductors

Transistors based on III-V semiconductor materials have been used for a variety of analog and high frequency applications driven by the high electron mobilities in III-V materials. On the other hand, the hole mobility in III-V materials has always lagged compared to group-IV semiconductors such as silicon and germanium. In this paper we explore the used of strain and heterostructure design guided by bandstructure modeling to enhance the hole mobility in III-V materials. Parameters such as strain, valence band offset, effective masses and splitting between the light and heavy hole bands that are important for optimizing hole transport are measured quantitatively using various experimental techniques. A peak Hall mobility for the holes of 960cm2/Vs is demonstrated and the high hole mobility is maintained even at high sheet charge.Comment: 18 pages, 21 figure