Low-voltage CMOS log-companding techniques for audio applications

This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of μA) complete SoCs in CMOS technologies. The new design proposal is based on both, the Log Companding theory and the MOSFET operating in subthreshold. Several basic building blocks for audio amplification, AGC and arbitrary filtering are given. The feasibility of the proposed CMOS circuits is illustrated through experimental data for different design case studies in 1.2 and 0.35 μm VLSI technologies.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99- 1084European Union ESPRIT-FUSE-2306

Novel Bandpass Filter Design based on Synchronous Filtering

The design of high-performance low-noise bandpass filtering systems has been studied from several aspects: (1) applying the synchronous filtering idea to the development of externally linear, time-invariant filters which can be internally nonlinear and/or time-varying, (2) seeking solutions to improve the noise performance of these filters, from parameter configuration to architecture design, and (3) implementing the systems of interest as transistor level circuits and verifying their function.Particularly, the state space representations for a biquad AM mode synchronous bandpass filter and a biquad FM mode synchronous complex filter have been proposed and realized with ideal Gm-C networks and log-domain circuits. Both systems utilize the modulator-core filter-modulator architecture to synchronize the internal signal processing. The core filter in an AM mode synchronous filter has constant center frequency and time-variant bandwidth, and the terminal modulators perform amplitude modulation to maintain the system’s external linearity and input/output characteristics. An FM mode synchronous filter typically has time-invariant bandwidth and performs frequency modulation before and after the signal filtering. Depending on whether the center frequency and terminal modulating frequency vary with time, there are static and dynamic types of FM mode synchronous filters. They both have the advantage of being able to filter the high frequency input signals in a low frequency range, which greatly alleviates the design and integration challenge due to the high frequency limitation of active components. Moreover, some dynamic filters effectively suppress the injected single-tone noise and generate an output with much higher SNR in comparison to the output from a static filter that implements the same transfer function.As a variation of an AM mode synchronous bandpass filter, the system derived by removing its back end modulator has been verified to have impressive noise reduction capability when processing noisy AM signals. Furthermore, it inspired the development of a feedback filtering system, the effective bandwidth of which could be tuned by scaling the feedback signal that time varies the core filter’s instantaneous bandwidth. It further provides an innovative approach to the design of a high-Q filter with superior immunity to internal noise, using a filter with very low Q factor. Finally, a design that combines the feedback architecture and the biquad FM mode synchronous complex filter is proposed and implemented as a log-domain filtering circuit. Appealing features of this system include wide dynamic range, flexible bandwidth and center frequency tunability. Since there is a low requirement for the high-frequency performance of active components, these filters make a good fit for monolithic integration, and greatly improved immunity to in-filter noise in comparison to that of an open loop complex filter with similar external filtering capability

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Analogue filter networks: developments in theory, design and analyses

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