Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Excimer Laser Crystallization of Silicon Thin-Films for Monolithic 3D Integration

In 1964 the first metal oxide semiconductor (MOS) integrated circuit (IC) became available. Shortly after in 1965 Gordon Moore predicted the pace of the device density increase in ICs. His prediction became a self-fulfilling prophecy, which taking advantage of the formal device scaling rules introduced by Robert Dennard in 1974, drove the evolution of the integrated electronic industry. In conventional two dimensional ICs, devices are integrated into a single layer of silicon in what is called the front end of line (FEOL) fabrication. Additional layers on top of the devices serve as inter-dielectric isolating layer and metal interconnects and are fabricated in the back end of line (BEOL) process. Scaling the dimension of devices allows for an increase in device density, improvement on device switching speed and reduction of the cost per device. The conjunction of these benefits drove the industry thus far. Over the past decade further scaling the devices while achieving also an increase in performance and cost benefits became extremely difficult. As the dimensional scaling of complementary MOS (CMOS) devices reaches its limits, three dimensional ICs (3DICs) are increasingly being considered as a path to achieve higher device densities. 3DICs offer a way to increase density by using multiple device layers on the same die, reducing the interconnect distance and allowing for a decrease in signal delay. Among different fabrication techniques, monolithic 3D integration is potentially more cost effective but requires high performance devices, a process compatible with transistor integration in the BEOL stack and needs to deliver a high device density and uniformity in order to be adopted by the very large scale integration (VLSI) industry. This work focuses on a particular laser crystallization technique to achieve monolithic device integration. The technique, called Excimer Laser Crystallization (ELC), makes use of an excimer laser to achieve a large grain polycrystalline thin-film starting from an amorphous layer, allowing integration of high quality thin-film transistors (TFTs). Thus far, the ELC technique has been studied on thin-films typically deposited on top of quartz substrate or Si/SiO₂ wafers. On the other hand state of the art VLSI integration uses more advance BEOL stacks with low-κ material as interlayer dielectrics (ILDs) to passivate the copper (Cu) interconnect lines. This thesis focuses on three different key aspect to enable laser crystallization in the BEOL for device integration: 1. Excimer laser crystallization of amorphous silicon on low-κ dielectric; 2. Excimer laser crystallization of amorphous silicon on BEOL processed wafer; 3. VLSI of TFTs on excimer laser crystallized silicon. The ELC of amorphous silicon on low-κ dielectric is first explored through one dimension (1D) finite element method (FEM) simulation of the temperature evolution during the laser exposure in two different systems: 1. amorphous silicon deposited on top of SiO₂ dielectric; 2. amorphous silicon deposited on top of low-κ dielectric. Simulations predict that is necessary a lower laser energy for crystallizing the silicon on the low-κ material. Experimental observations confirm the predicted behavior yielding a 35% lower energy for crystallization of thin-film silicon on top of a low-κ dielectric. Material characterization through defect enhanced SEM micrograph, Raman spectroscopy and XRD analysis shows an equivalent material morphology for the two system with a preferential (111) crystal orientation for the SiO₂ system. Silicon crystallization on BEOL processed wafer is studied through a combination of 1D FEM simulation and experimental observation on a silicon layer deposited on top of a SiO₂dielectric protecting the underlying damascene Cu structure. 1D FEM show that during the silicon laser exposure, because of the short pulse width of the laser (30 ns), the heat is retained in the amorphous silicon layer allowing its melting while keeping the temperature of the Cu lines below 320 °C which is a favorable condition for monolithic integration in the BEOL. Further experimental evidences show the ability of crystallizing a-Si on such structure while preserving the physical and electrical properties of the Cu lines. The feasibility of monolithic VLSI 3D integration is demonstrated through integration of TFTs devices on 200 mm silicon wafers. The integration process and performance of the TFTs device are modeled through technology computer aided design (TCAD) simulations which are used to define the process flow and the fabrication parameters. Characterization of the TFTs over multiple die yield good device performance and uniformity. TFTs characterized with 1.5 V of supply voltage have a sub-threshold slope down to 79 mV/decade, current density up to 26.3 μA/μm, a threshold voltage of 0.23 V, current On/Off ratio above 10⁵ and device field effect mobility up to 19.8 cm²/(V s) for LPCVD-sourced silicon. Furthermore, the Levinson method allows characterization of the trap density in the thin-film polysilicon devices yielding a mean value 8.13×10¹² cm². This work present an integration scheme which proves to be compatible with VLSI in the BEOL of wafers. It paves the way to further development which could lead to an high performance, cost effective, monolithic 3D integration approach useful in application such as reconfigurable logic, display, heterogeneous integration and on chip optical communications

Thin‐Film Transistors for Large Area Opto/Electronics

The present work addresses several issues in the field of organic and transparent electronics. One of them is the prevailing high power consumption in state-of-the-art organic field-effect transistors (OFETs). A possible solution could be the implementation of complementary, rather than unipolar logic, but this development is currently inhibited by a distinct lack of high performance electron transporting (n-channel) OFETs. Here, the issue is addressed by investigating a series of solution processable n-channel fullerene molecules in combination with optimized transistor architectures. Furthermore, the trend towards complementary circuit design could be facilitated by employing ambipolar organic semiconductors, such as squaraine molecules or polymer/fullerene blends. These materials can fill the role of p- or n-channel semiconductors and enable the facile implementation of power saving complementary-like logic, eliminating the cost-intensive patterned deposition of discrete p-and n-channel transistors. Alternatively, a patterning method for organic materials adapted from standard photolithography is discussed. Furthermore, ambipolar FETs are found to be capable of light sensing at wavelength of 400-1000 nm. Hence their use in low-cost, organic based optical sensor arrays can be envisioned. Another strategy to reduce the power consumption and operating voltages of OFETs is the use of ultra-thin, self-assembled molecular gate dielectrics, such as alkyl-phosphonic acid molecules. Based on this approach solution processed n- and p-channel OFETs and a complementary organic inverter circuit are demonstrated, which operate at less than 2 Volts. Finally, transparent oxide semiconductors are investigated for use in thin-film transistors. Titanium dioxide (TiO2) and zinc oxide (ZnO) films are deposited by means of a low-cost large area compatible spray pyrolysis technique. ZnO transistors exhibit high electron mobility of the order of 10 cm2/Vs and stable operation in air at less than 2 Volts. These results are considered significant steps towards the development of organic and transparent large-area optoelectronics

hybrid materials for integrated photonics

In this review materials and technologies of the hybrid approach to integrated photonics (IP) are addressed. IP is nowadays a mature technology and is the most promising candidate to overcome the main limitations that electronics is facing due to the extreme level of integration it has achieved. IP will be based on silicon photonics in order to exploit the CMOS compatibility and the large infrastructures already available for the fabrication of devices. But silicon has severe limits especially concerning the development of active photonics: its low efficiency in photons emission and the limited capability to be used as modulator require finding suitable materials able to fulfill these fundamental tasks. Furthermore there is the need to define standardized processes to render these materials compatible with the CMOS process and to fully exploit their capabilities. This review describes the most promising materials and technological approaches that are either currently implemented or may be used in the coming future to develop next generations of hybrid IP devices

A study on the role of dielectric and its interface in the performances of Organic Thin-Film Transistor

2009 - 2010Organic Thin-Film Transistor (OTFT) can be considered one of the building blocks of Organic Large-Area Electronics. The role of this kind of switching device is crucial in the organic information displays field but also in a wide range of possible applications which take advantage of such switching devices. For these reasons, major technology investments have been made to optimize the characteristics related to switching the power status of the pixel in order to obtain sufficient dynamics for a proper representation of moving pictures, movies, etc. In addition to technological and industrial fallouts of OTFT utilization, it should be noted that materials science in Organic Electronics often employs these transistors as an investigation method - an experiment – in order to characterize the physical properties of semiconductors, insulators and interfaces by leveraging device’ principles of operation and physics. The motivation of the present investigation is related to the evidence that gate dielectrics properties and dielectric-semiconductor interface physics are known to govern growth of partiallyordered channel films with a tremendous impact on the morphology of their polycrystalline phase and then to electric performances. Such relationships are still not clearly understood nor fully exploited in a wide spectrum of cases. Keeping in mind that gate insulators can be considered as a key-factor in OTFT device modeling and optimization, the purpose of this thesis work has been the analysis and the interpretation of the role played by such dielectrics and their interface in the organic thin-film transistors performance. The key aspects which have been investigated about dielectrics are the gate leakages and the models to extract the channel current, the relationship between wettability of dielectric surfaces and the growth of pentacene, the channel morphology, charge transport and its thermal activation. In particular, device’ operation regimes and performance parameters have been studied taking into account non-ideal behaviours which can hardly affect physical interpretations of charge transport mechanisms in organic semiconducting films and bring to misleading considerations. In such analysis, the parasitic gate dielectric conduction has been emphasized because it appears appealing both from a scientific point and from an industrial perspective. In fact, gate leakages often appear as a hidden problem in many literature reports and nevertheless they become dominant in technological considerations because they have a relevant impact when working on very thin insulating films or leaky dielectrics like polymers or solution-processed materials because they are responsible of static dissipation in OFET-based circuitry. In order to obtain improved devices, we studied the OTFT performances when varying the dielectric material. We considered the surface wettability as a key factor to be decreased in order to obtain performing channels. Thus, after taking into account standard gate dielectrics at different film thicknesses, and studying mobility in a gate-leakage-aware modeling framework, we acted on the nature and interface of insulators to increase the hydrophobicity and obtain a large-grain growth of pentacene channel semiconductor. In the experimental, among other things, we compared the utilization of highly hydrophobic compounds in gate dielectric layer fabrication to surface conditioning treatments of usual insulating polymers and to the deposition of buffer layers. In the aim to prepare an improved device, we introduced in device’ processing a novel insulating material, an organic-inorganic hybrid material based on a Tetraethyl Orthosilicate / 1H,1H,2H,2H-Perfluorodecyl triethoxysilane solution commonly named “PFTEOS:TEOS”. The abovementioned layer is characterized by perfluoroalkyl units which are responsible of the desired highly hydrophobic properties. It has been solutionprocessed and finally deposited by a spin-coating-based sol-gel technique on the metallic gate layer. Following an optimization path, a thin film (<10nm) of Poly(methyl methacrylate) has been employed to bufferize the PFTEOS:TEOS surface to reduce gate currents. A mobility-morphology trend for analyzed dielectrics in OTFTs has been extrapolated and analyzed denoting PFTEOS:TEOS as an exception to a well-assessed empirical rule. Escaping from obvious considerations about the effect of grain boundaries in channel performances, the singularity of PFTEOS:TEOS has lead to the adoption of thermal activation of charge carriers as an instrument to open to a deeper interpretation of channel defects. Thermal analyses of charge transport activation for the considered samples have been performed showing a general validity of the Meyer-Neldel rule also for hybrid dielectrics. Furthermore, the extraction of energetic parameters in Arrhenius plots applied to static electrical characterizations has revealed differences of maximum mobility trends versus the Meyer-Neldel characteristic Energy (EMN) when comparing polymer dielectric-based OTFTs to PFTEOS:TEOSbased OTFTs. The differences in dielectric/OSC interface appared to be correlated to the isokinetic temperature and activation energy and then to the disorder parameter “:” of the Density Of States in the valence band of the organic channel. Then, instead of considering the contribution of inband density of states of the channel material, the amplitude of the distribution of energetic states has been exploited in the investigation of surface properties and dielectric-specific features remarked. The activation energy analysis showed a trend inversion in the Meyer-Neldel Temperature (TMN)/mobility relationship between PMMA samples and PFTEOS:TEOS samples revealing an effect induced by the very nature of insulator rather than the OSC/dielectric interface on thermally activated processes. The dielectric is then acknowledged to be responsible of a wide range of thermally-activated behaviours in the response of disordered OSC used in OTFTs. Then, thermal analyses have proven to be a key discriminant factor to address non-conventional dielectrics surface-features characterizations in electronic devices able to quantify nanoscopic disorder in polycristalline mediums. In conclusion the behavior of a novel sol-gel gate insulator has been characterized and analyzed comparing it to plain cases and finding an original behavior of mobility/Activation energy which exhibits an inverse (decreasing) trend between energetic disorder and charge transport. This has been completely opposite to trends found for PMMA devices encouraging studying, exploiting and characterizing more in depth PFTEOS:TEOS material for OTFT fabrication purposes. Organic Electronics has still to face some key challenges to assert itself and become competitive in market sectors left still partially unexplored by the inorganic electronic technology. From this point of view, the possibility to exploit dielectric materials singularities to break technological performance trends, united to the availability of second-order modelling techniques both in insulator non-idealities and in charge transport activation can be a non-trivial starting point for further investigations.[edited by author]IX n.s

Solution processed low power organic field-effect transistor bio-chemical sensor of high transconductance efficiency

Developing organic field-effect transistor (OFET) biosensors for customizable detection of biomarkers for many diseases would provide a low-cost and convenient tool for both biological studies and clinical diagnosis. In this work, design principles of the OFET transducer for biosensors were derived to relate the signal-to-noise ratio (SNR) to the device-performance parameters. Steep subthreshold swing (SS), proper threshold voltage (Vth), good-enough bias-stress stability, and mechanical durability are shown to be the key prerequisites for realizing OFET bio-sensors of high transconductance efficiency (gm/ID) for large SNR. Combining a low trap-density channel and a high-k/low-k gate dielectric layer, low-temperature (<100 °C) solution-processed flexible OFETs can meet the performance requirements to maximize the gm/ID. An extended gate-structure OFET biosensor was further implemented for label-free detection of miR-21, achieving a detection limit below 10 pM with high selectivity at a low operation voltage (<1 V)

Hybrid Materials for Integrated Photonics

In this review materials and technologies of the hybrid approach to integrated photonics (IP) are addressed. IP is nowadays a mature technology and is the most promising candidate to overcome the main limitations that electronics is facing due to the extreme level of integration it has achieved. IP will be based on silicon photonics in order to exploit the CMOS compatibility and the large infrastructures already available for the fabrication of devices. But silicon has severe limits especially concerning the development of active photonics: its low efficiency in photons emission and the limited capability to be used as modulator require finding suitable materials able to fulfill these fundamental tasks. Furthermore there is the need to define standardized processes to render these materials compatible with the CMOS process and to fully exploit their capabilities. This review describes the most promising materials and technological approaches that are either currently implemented or may be used in the coming future to develop next generations of hybrid IP devices

Non-volatile organic memory devices: from design to applications

The research activity described in the attached dissertation focused on the development, fabrication and characterization of new non-volatile memory elements based on organic technology. During the last few decades, organic materials based devices have attracted considerable interest due to their great potential for future electronic systems. Low fabrication costs, high mechanical flexibility and versatility of the chemical structure, good scalability and easy processing are the unique advantages of organic electronics. As memory devices are essential elements of any kind of electronic system, the development of organic memory devices is fundamental in order to extend the application of organic materials to different electronic circuits. Research on organic electronic memories is currently at a rapid growth stage, since it is recognized that they may be an alternative or supplementary to the conventional memory technologies. Despite considerable progress in the advancement of novel memory technologies in recent years, some challenging tasks still need to be resolved. The Ph.D. research activity of this thesis is related to the still -opened challenges in the organic memories technologies. In particular, it focused mainly on the study, development, fabrication and characterization of new non-volatile organic memory elements based on resistive switching. The activity has been carried out in the frame of the European project “HYbrid organic/inorganic Memory Elements for integration of electronic and photonic Circuitry” (HYMEC), which involved the University of Cagliari during the last three years. The project goal was to realize new hybrid inorganic/organic resistive memory devices with functionality far beyond the state of the art. A complementary activity on transistor-based organic memory devices has been also carried out and described in this thesis. As regards resistive memory devices, the research activity included design, fabrication and testing of a novel non-volatile memory device based on the combination of an air-stable organic semiconductor and metal nanoparticles. This topic required the development of technology and procedures for easy and reliable production of devices as well as the definition of measurement protocols. The proposed structure was thoroughly characterized by morphological techniques, which allowed to interpret the resistive switching mechanisms in terms of formation and rupture of metallic filaments inside the organic layer assisted by the metal NPs. The obtained performances are the best reported so far in literature, and, to our knowledge, the statistics analysis is the largest ever reported for organic-based resistive memories. The developed technology was then successfully applied on flexible plastic substrates. The definition of technological processes for the reliable fabrication of high performance printed organic memory devices was also carried out: this work clearly demonstrates the real possibility of fabricating high performance printed memory elements. A significant effort was also devoted to the development of basic memory/sensor systems entirely fabricated on plastic substrates. The suitability of organic non-volatile memory devices for the detection and the storage of external parameters was demonstrated. The results definitely demonstrated the feasibility of the proposed technology for the fabrication of systems including organic memories for their final application in different industrial processes, including e-textile and smart packaging. As regards transistor memory devices, highly flexible Organic Field-Effect Transistor (OFET)-based memory elements with excellent mechanical stability and high retention time were developed. As main innovation with respect to the state of the art, low voltage operation of the OFET-based memory was investigated. Such an activity was also related to the development of reliable measurement procedure