Programmable photonic circuits

[EN] The growing maturity of integrated photonic technology makes it possible to build increasingly large and complex photonic circuits on the surface of a chip. Today, most of these circuits are designed for a specific application, but the increase in complexity has introduced a generation of photonic circuits that can be programmed using software for a wide variety of functions through a mesh of on-chip waveguides, tunable beam couplers and optical phase shifters. Here we discuss the state of this emerging technology, including recent developments in photonic building blocks and circuit architectures, as well as electronic control and programming strategies. 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Miniature Multilevel Optical Memristive Switch Using Phase Change Material

Optical memristive switches can be used as optical latching switches in which the switching state is changed only by applying an electrical Write/Erase pulse and maintained without an external power supply. We demonstrate an optical memristive switch based on a silicon multimode interferometer structure covered with nanoscale-sized Ge2Sb2Te5 (GST) material on top. The phase change of GST is triggered by resistive heating of the silicon layer beneath GST with an electrical pulse. Experimental results reveal that the optical transmissivity can be tuned in a controllable and repeatable manner. Partial crystallization of GST is obtained by controlling the width and amplitude of the electrical pulses. Crucially, we demonstrate that both Erase and Write operations, to and from any intermediate level, are possible with accurate control of the electrical pulses. Our work marks a significant step forward toward realizing photonic memristive switches without static power consumption, which are highly demanded in integrated photonics

Silicon photonic MEMS switches based on split waveguide crossings

The continuous push for high-performance photonic switches is one of the most crucial premises for the sustainable scaling of programmable and reconfigurable photonic circuits for a wide spectrum of applications. Large-scale photonic switches constructed with a large number of 2$\times$2 elementary switches impose stringent requirements on the elementary switches. In contrast to conventional elementary switches based on mode interference or mode coupling, here we propose and realize a brand-new silicon MEMS 2$\times$2 elementary switch based on a split waveguide crossing (SWX) consisting of two halves. With this structure, the propagation direction of the incident light can be manipulated to implement the OFF and ON states by splitting or combining the two halves of the SWX, respectively. More specifically, we introduce refractive-index engineering by incorporating subwavelength-tooth (SWT) structures on both reflecting facets to further reduce the excess loss in the ON state. Such a unique switching mechanism features a compact footprint on a standard SOI wafer and enables excellent photonic performance with low excess loss of 0.1-0.52/0.1-0.47dB and low crosstalk of $\lt$-37/-22.5dB over an ultrawide bandwidth of 1400-1700nm for the OFF/ON states in simulation, while in experiment, excess loss of 0.15-0.52/0.42-0.66dB and crosstalk of $\lt$-45.5/-25dB over the bandwidth of 1525-1605 nm for the OFF/ON states have been measured.Furthermore, excellent MEMS characteristics such as near-zero steady-state power consumption, low switching energy of sub-pJ, switching speed of {\mu}s-scale, durability beyond 10^9 switching cycles, and overall device robustness have been achieved. Finally, a 16$\times$16 switch using Benes topology has also been fabricated and characterized as a proof of concept, further validating the suitability of the SWX switches for large-scale integration

Silicon Photonic Subsystems for Inter-Chip Optical Networks

The continuous growth of electronic compute and memory nodes in terms of the number of I/O pins, bandwidth, and areal throughput poses major integration and packaging challenges associated with offloading multi-Tbit/s data rates within the few pJ/bit targets. While integrated photonics are already deployed in long and short distances such as inter and intra data centers communications, the promising characteristics of the silicon photonic platform set it as the future technology for optical interconnects in ultra short inter-chip distances. The high index contrast between the waveguide and the cladding together with strong thermo-optic and carrier effects in silicon allows developing a wide range of micro-scale and low power optical devices compatible with the CMOS fabrication processes. Furthermore, the availability of photonic foundries and new electrical and optical co-packaging techniques further pushes this platform for the next steps of commercial deployment. The work in this dissertation presents the current trends in high-performance memory and processor nodes and gives motivation for disaggregated and reconfigurable inter-chip network enabled with the silicon photonic layer. A dense WDM transceiver and broadband switch architectures are discussed to support a bi-directional network of ten hybrid-memory cubes (HMC) interconnected to ten processor nodes with an overall aggregated bandwidth of 9.6Tbit/s. Latency and energy consumption are key performance parameters in a processor to primary memory nodes connectivity. The transceiver design is based on energy-efficient micro-ring resonators, and the broadband switch is constructed with 2x2 Mach-Zehnder elements for nano-second reconfiguration. Each transceiver is based on hundreds of micro-rings to convert the native HMC electrical protocol to the optical domain and the switch is based on tens of hundreds of 2x2 elements to achieve non-blocking all-to-all connectivity. The next chapters focus on developing methods for controlling and monitoring such complex and highly integrated silicon photonic subsystems. The thermo-optic effect is characterized and we show experimentally that the phase of the optical carrier can be reliably controlled with pulse-width modulation (PWM) signal, ultimately relaxing the need for hundreds of digital to analog converters (DACs). We further show that doped waveguide heaters can be utilized as \textit{in-line} optical power monitors by measuring photo-conductance current, which is an alternative for the conventional tapping and integration of photo-diodes. The next part concerned with a common cascaded micro-ring resonator in a WDM transceiver design. We develop on an FPGA control algorithm that abstracts the physical layer and takes user-defined inputs to set the resonances to the desired wavelength in a unicast and multicast transmission modes. The associated sensitivities of these silicon ring resonators are presented and addressed with three closed-loop solutions. We first show a closed-loop operation based on tapping the error signal from the drop port of the micro-ring. The second solution presents a resonance wavelength locking with a single digital I/O for control and feedback signals. Lastly, we leverage the photo-conductance effect and demonstrate the locking procedure using only the doped heater for both control and feedback purposes. To achieve the inter-chip reconfigurability we discuss recent advances of high-port-count SiP broadband switches for reconfigurable inter-chip networks. To ensure optimal operation in terms of low insertion loss, low cross-talk and high signal integrity per routing path, hundreds of 2x2 Mach-Zehnder elements need to be biased precisely for the cross and bar states. We address this challenge with a tapless and a design agnostic calibration approach based on the photo-conductance effect. The automated algorithm returns a look-up table for all for each 2x2 element and the associated calibrated biases. Each routing scenario is then tested for insertion loss, crosstalk and bit-error rate of 25Gbit/s 4-level pulse amplitude modulation signals. The last part utilizes the Mach-Zehnder interferometers in WDM transceiver applications. We demonstrate a polarization insensitive four-channel WDM receiver with 40Gbit/s per channel and a transmitter design generating 8-level pulse amplitude modulation signals at 30Gbit/s

Development of Silicon Photonic Multi Chip Module Transceivers

The exponential growth of data generation–driven in part by the proliferation of applications such as high definition streaming, artificial intelligence, and the internet of things–presents an impending bottleneck for electrical interconnects to fulfill data center bandwidth demands. Links now require bandwidths in excess of multiple Tbps while operating on the order of picojoules per bit, in addition to constraints on areal bandwidth densities and pin I/O bandwidth densities. Optical communications built on a silicon photonic platform offers a potential solution to develop power efficient, high bandwidth, low attenuation, small footprint links, all while building off the mature CMOS ecosystem. The development of silicon photonic foundries supporting multi project wafer runs with associated process design kit components supports a path towards widespread commercial production by increasing production volume while reducing fabrication and development costs. While silicon photonics can always be improved in terms of performance and yield, one of the central challenges is the integration of the silicon photonic integrated circuits with the driving electronic integrated circuits and data generating compute nodes such as CPUs, FPGAs, and ASICs. The co-packaging of the photonics with the electronics is crucial for adoption of silicon photonics in datacenters, as improper integration negates all the potential benefits of silicon photonics. The work in this dissertation is centered around the development of silicon photonic multi chip module transceivers to aid in the deployment of silicon photonics within data centers. Section one focuses on silicon photonic integration and highlights multiple integrated transceiver prototypes. The central prototype features a photonic integrated circuit with bus waveguides with WDM microdisk modulators for the transmitter and WDM demuxes with drop ports to photodiodes for the receiver. The 2.5D integrated prototype utilizes a thinned silicon interposer and TIA electronic integrated circuits. The architecture, integration, characterization, performance, and scalability of the prototype are discussed. The development of this first prototype identified key design considerations necessary for designing multi chip module silicon photonic prototypes, which will be addressed in this section. Finally, other multi chip module silicon photonic prototypes will be overviewed. These include a 2.5D integrated transceiver with a different electronic integrated circuit TIA, a 3D integrated receiver, an active interposer network on chip, and a 2.5D integrated transceiver with custom electronic integrated circuits. Section two focuses on research that supports the development of silicon photonic transceivers. The thermal crosstalk from neighboring microdisk modulators as a function of modulator pitch is investigated. As modulators are placed at denser pitches to accommodate areal bandwidth density requirements in transceivers, this thermal crosstalk will become significant. In this section, designs and results from several iterations of custom microring modulators are reported. Custom microring modulators allow for scaling up the number of channels in microring transceivers by offering the ability to fabricate variable resonances and provide a platform for further innovation in bandwidth, free spectral range, and energy efficiency. The designs and results of higher order modulation format modulators, both microring based and Mach Zehnder based, are discussed. High order modulators offer a path towards scaling transceiver total throughput without having to increase the channel counts or component bandwidth. Together, the work in these two sections supports the development of silicon photonic transceivers to aid in the adoption of silicon photonics into data generating systems